Stacked Nanowire Gate Electrodes for Back-Bias Leakage Reduction
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Solution Overview
Problem
Nanowire FETs fail to apply a back bias to the channel formation region, limiting their ability to reduce leakage current while improving performance.
Innovation Solution
A semiconductor device with a stacked structure of channel formation and gate electrode layers, where odd-numbered gate electrode layers are connected to a first contact portion and even-numbered layers to a second contact portion, allowing application of different voltages to reduce leakage current and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gate electrodes surround the periphery of the nanowire-structured channel formation region, then the transistor drive capability is improved, but the ability to apply back bias is lost and leakage current cannot be reduced
Solution Approach 1:
The gate electrode structure is segmented into multiple distinct gate electrodes (first gate electrode and second gate electrode) positioned at different locations relative to the channel formation region. This segmentation allows independent voltage control of each gate electrode, enabling the application of back bias to the channel formation region while maintaining drive capability through proper voltage configuration on the gate electrodes.
2Length of moving object
If the silicon layer thickness is reduced for FET miniaturization, then the device size is reduced, but the silicon layer reaches a technical limit of 5-nm thickness
Solution Approach 1:
The invention transitions from a planar silicon layer structure to a three-dimensional nanowire structure. The nanowire channel formation region extends in the vertical dimension with a diameter of 3 nm or less, allowing continued miniaturization beyond the 5-nm thickness limit of planar silicon layers. This dimensional change enables further scaling while maintaining structural integrity and electrical performance.
Data Source
AI summary
A semiconductor device includes a stacked structure having channel formation region layers CH1 and CH2, gate electrode layers G1, G2, and G3 alternately arranged on a base, in which a lowermost layer of the stacked structure is formed with a 1st layer G1 of the gate electrode layers, an uppermost layer of the stacked structure is formed with an Nth (where N≥3) layer G3 of the gate electrode layers, the gate electrode layers each have a first end face, a second end face, a third end face opposing the first end face, and a fourth end face opposing the second end face, the first end face of odd-numbered layers G1, G3 of the gate electrode layers is connected to a first contact portion, and the third end face of an even-numbered layer G2 of the gate electrode layers is connected to a second contact portion.