Stacked Gate Electrodes with Voids for Semiconductor Memory Capacity
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity effectively, particularly in electronic systems that require high-capacity data storage, as traditional two-dimensional memory cell arrangements are limited in their storage capabilities.
Innovation Solution
The semiconductor memory device incorporates a cell substrate with stacked gate electrodes, including voids, and channel structures that penetrate these electrodes, utilizing molybdenum materials and a specific arrangement of block separation structures to enhance data storage capacity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged two-dimensionally, then the device structure is simple and easy to manufacture, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked gate electrode structure. Multiple gate electrodes are stacked vertically over the cell substrate, with channel structures penetrating through the stack, enabling increased storage capacity by utilizing the vertical dimension while maintaining manufacturability through established semiconductor fabrication processes
2Quantity of substance
If gate electrodes are made solid without voids, then the structural strength is high, but the data storage capacity is reduced
Solution Approach 1:
The patent introduces voids (empty spaces) within the gate electrode structures between adjacent channel structures. These voids increase the effective storage capacity by allowing additional charge trapping or insulation functionality while the surrounding molybdenum material and overall gate electrode framework maintain sufficient structural strength
Solution Approach 2:
The gate electrodes are formed using molybdenum material with integrated void spaces, creating a composite structure that combines the high strength and conductivity of molybdenum with the storage-enhancing void regions, achieving both mechanical integrity and increased storage capacity
3Quantity of substance
If voids are placed on all gate electrodes including those between block separation structure and channel structure, then the data storage capacity is maximized, but the reliability is reduced
Solution Approach 1:
The patent applies voids selectively only to gate electrodes positioned between adjacent channel structures, while excluding gate electrodes located between the block separation structure and adjacent channel structures. This localized application maintains high storage capacity in the channel regions while preserving structural integrity and reliability at the block separation interfaces where voids could compromise mechanical support
Data Source
AI summary
A semiconductor memory device includes a cell substrate including a cell array region and an extended region, gate electrodes stacked on the cell substrate, the gate electrodes including molybdenum, and channel structures in the cell array region, the channel structures penetrating the gate electrodes, wherein at least one of the gate electrodes includes at least one void in a region between the channel structures.