Stacked Gate Layer Etching for Higher-Density Semiconductor Memory
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Solution Overview
Problem
The increasing demand for improved price competitiveness of semiconductor devices necessitates enhanced integration levels, which is hindered by interference between data storage regions and gate structures in stacked semiconductor devices.
Innovation Solution
A method of forming a semiconductor device involves creating a mold structure with alternately stacked interlayer insulating layers and gate layers of different etch selectivity materials, forming extended holes with recessed regions, and constructing memory vertical structures within these holes to reduce interference and increase integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stacking number of gates is increased to improve integration, then the degree of integration is improved, but interference between data storage regions opposing the gates is increased
Solution Approach 1:
The gate layer is segmented into multiple sub-layers (first gate sub-layer, second gate sub-layer, third gate sub-layer) with different materials and etch selectivities. This segmentation allows selective removal of specific gate portions to create spaced-apart gate structures, reducing interference between opposing data storage regions while maintaining high integration through vertical stacking.
Solution Approach 2:
Different portions of the gate layer are assigned different local qualities through using distinct materials (e.g., first material for first and third sub-layers, second material for second sub-layer) with different etch selectivities. This enables localized modification of gate structures in specific regions to minimize interference while preserving functionality in other regions.
2Object-affected harmful factors
If gates are stacked while being spaced apart to reduce interference, then interference between data storage regions is reduced, but device complexity is increased
Solution Approach 1:
The gate structure employs a nested doll approach where multiple gate sub-layers are stacked within each other, with each sub-layer having different etch selectivity. The first, second, and third gate sub-layers are nested sequentially, allowing selective etching to create the spaced-apart configuration while maintaining a relatively simple overall fabrication process.
Solution Approach 2:
The invention changes material parameters by selecting materials with different etch selectivities for different gate sub-layers. This parameter change enables selective removal of specific gate portions through etching processes, creating the desired spaced-apart structure without requiring complex lithographic patterning or additional fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the degree of integration by minimizing interference between data storage regions and gate structures, thereby improving the performance and efficiency of semiconductor devices.
Implementation Method 1
the second layer including a second material having an etch selectivity different from an etch selectivity of the first material; forming the hole as an extended hole, the forming the hole as the extended hole including forming recessed regions by partially etching the gate layers, exposed by the hole, by performing an etching process in which an etching speed of the second material is different from an etching speed of the first material
Data Source
AI summary
A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.