Vertical Memory Channel Liner for GIDL Erase in Stacked Gates
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density and efficiently performing erasing operations, particularly due to limitations in transistor structure and material impurity distribution.
Innovation Solution
A vertical-type memory device is designed with a vertical channel structure and gate electrodes, incorporating a liner with high n-type impurities to utilize the gate-induced drain leakage (GIDL) phenomenon for erasing operations, enhancing integration density and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical-type transistor structure is used to increase integration density, then the integration density is improved, but the erasing operation capability is worsened
Solution Approach 1:
The patent applies local quality by introducing a liner with high n-type impurities specifically in the upper portion of the channel structure, rather than uniformly distributing impurities throughout. This localized doping creates the necessary conditions for GIDL phenomenon to occur in the upper gate region, enabling erasing operation capability while maintaining the vertical transistor structure for high integration density.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a liner with high n-type impurities in the upper channel portion. This parameter change enables the GIDL phenomenon to occur, which provides the erasing operation capability that was previously lost in vertical-type structures. The impurity concentration is specifically tailored to facilitate hole generation and extraction during erasing operations.
2Ease of operation
If conventional planar transistor structure is used, then erasing operation is easier to perform, but integration density is reduced
Solution Approach 1:
The patent transitions from a conventional planar (2D) transistor structure to a vertical (3D) transistor structure with a vertical channel extending in the thickness direction. This dimensional change allows multiple gate electrodes to be stacked vertically, significantly increasing integration density while maintaining erasing operation capability through the added liner structure with high n-type impurities.
Solution Approach 2:
The patent implements nesting by placing multiple gate electrodes (first gate electrode, second gate electrode, etc.) in a vertical stack configuration. The liner with high n-type impurities is nested within the channel structure, specifically positioned to enable GIDL phenomenon. This nested arrangement allows compact vertical stacking that increases integration density while preserving operational capabilities.
3Ease of manufacture
If uniform impurity distribution is used in the channel, then manufacturing is simpler, but GIDL phenomenon cannot be effectively utilized for erasing
Solution Approach 1:
The patent applies local quality by introducing a liner with high n-type impurities specifically in the upper portion of the channel structure, rather than uniformly distributing impurities throughout. This localized doping creates the necessary conditions for GIDL phenomenon to occur in the upper gate region, enabling erasing operation capability while maintaining the vertical transistor structure for high integration density.
Solution Approach 2:
The patent segments the channel structure by introducing a distinct liner layer with high n-type impurities separate from the bulk channel material. This segmentation allows the upper portion of the channel to have different electrical properties (high n-type doping) compared to the rest of the channel, enabling GIDL phenomenon to occur specifically in the region where it is needed for erasing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables improved erasing capabilities and increased integration density in semiconductor memory devices by leveraging the GIDL phenomenon, thereby enhancing the reliability and productivity of memory devices.
Implementation Method 1
Example embodiments of the present inventive concept provide a vertical-type memory device capable of performing an erasing operation using a gate-induced drain leakage (GIDL) phenomenon by gate electrodes disposed in an upper portion among a plurality of gate electrodes.
Data Source
AI summary
A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.