Stacked Multi-Gate Heat Sink Structure for C-FET Heat Dissipation

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Solution Overview

Problem

Stacked multi-gate devices, such as complementary field effect transistors (C-FETs), face challenges in heat dissipation due to increased heat generation and the lack of an effective heat sink, particularly in vertical configurations where traditional heat dissipation methods are compromised.

Innovation Solution

The introduction of high thermal conductivity (high-Kappa) dielectric layers is used as a heat sink within the C-FET structure, either as bonding layers between semiconductor stacks or integrated within the superlattice structure, to effectively dissipate heat generated by the devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If stacked multi-gate devices are used to increase device density and performance, then functional density and gate control are improved, but heat generation increases and heat dissipation becomes difficult

Engineering Contradiction:
Improvedevice densityVSAvoidheat dissipation
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent introduces a heat sink structure as an intermediary component between the stacked multi-gate devices and the substrate. This heat sink includes a heat spreader layer in thermal contact with the devices and a heat dissipation structure extending toward the substrate, mediating the thermal transfer path and enabling effective heat management in the high-density stacked configuration

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces traditional substrate-based heat dissipation with a dedicated heat sink structure that uses thermally conductive materials (such as diamond, cubic boron nitride, or metal layers) to substitute the mechanical/thermal path through the substrate, creating an optimized thermal management system independent of the substrate material

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of manufacture

If traditional heat dissipation methods are used in vertical configurations, then manufacturing is simpler, but heat dissipation effectiveness is compromised

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidheat dissipation effectiveness
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent transitions from planar heat dissipation to three-dimensional vertical heat dissipation by extending the heat sink structure in the vertical dimension. The heat spreader layer contacts the devices horizontally while the heat dissipation structure extends vertically toward the substrate, utilizing the vertical space to create an effective thermal path without complicating the manufacturing process

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The incorporation of high-Kappa dielectric layers significantly improves heat spreading and dissipation in C-FET structures, addressing the heat management issues in stacked multi-gate devices and enhancing their thermal performance.

Implementation Method 1

The introduction of high thermal conductivity (high-Kappa) dielectric layers is used as a heat sink within the C-FET structure... to effectively dissipate heat generated by the devices

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240413039A1Heat sink for stacked multi-gate device
Publication Date: 2024.12.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240413039A1 patent drawing
  • US20240413039A1 patent drawing
  • US20240413039A1 patent drawing

AI summary

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a semiconductor substrate, a high-Kappa dielectric layer disposed on the semiconductor substrate, a first plurality of nanostructures disposed over the high-Kappa dielectric layer, a middle dielectric layer disposed over the first plurality of nanostructures, a second plurality of nanostructures over the middle dielectric layer, a first gate structure wrapping around the first plurality of nanostructures, a second gate structure wrapping around the second plurality of nanostructures. The high-Kappa dielectric layer includes metal nitride, metal oxide, silicon carbide, graphene, or diamond.