Stacked Semiconductor Gate Structure With High-k Spacer Leakage Control
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to increased integration, leading to challenges in achieving superior performance.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a gate electrode and high-k dielectric layer, along with an inner spacer that defines an inner gate space, is implemented. This design includes a gate dielectric layer with a high-k dielectric material surrounding the inner electrode and an inner spacer with specific thickness ratios, enhancing electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are scaled down to increase integration, then device density is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked semiconductor patterns (nanowire FETs), allowing multiple channels to be stacked in the vertical direction. This dimensional change enables increased device density without further scaling of the lateral dimensions, thereby maintaining operating characteristics while improving integration density.
Solution Approach 2:
The patent implements nested structures where gate electrodes and gate dielectric layers wrap around and surround the vertically stacked semiconductor channel patterns. The inner spacer is nested within the gate dielectric layer, and multiple semiconductor patterns are nested vertically within a single device footprint, achieving high density while preserving electrical performance.
2Ease of manufacture
If conventional gate structures are used in scaled devices, then manufacturing simplicity is maintained, but leakage current increases
Solution Approach 1:
The patent changes the dielectric parameter by introducing high-k dielectric materials with higher dielectric constants than conventional silicon dioxide. This parameter change allows the gate to achieve stronger electrical control over the channel with lower leakage current, while the surrounding gate structure provides additional control to suppress short-channel effects in the scaled devices.
Solution Approach 2:
The gate dielectric layer is constructed as a composite structure combining high-k dielectric materials with inner spacers made of different materials. This composite approach provides both low-leakage properties from the high-k material and additional electrical control from the inner spacer, reducing overall leakage current while maintaining manufacturability through established deposition and etching processes.
3Quantity of substance
If vertically stacked semiconductor patterns are implemented, then device density is improved, but gate dielectric layer uniformity becomes difficult to maintain
Solution Approach 1:
The patent forms the inner spacer structure before depositing the high-k gate dielectric layer. This preliminary action creates a predefined template that guides the subsequent dielectric deposition, ensuring uniform coverage of the complex three-dimensional semiconductor patterns. The inner spacer acts as a sacrificial or guiding structure that simplifies the formation of uniform gate dielectric on vertically stacked channels.
Solution Approach 2:
The gate dielectric system is segmented into multiple components: inner spacers positioned at specific locations and high-k dielectric layers covering the semiconductor patterns. This segmentation allows each component to be optimized and formed independently, with the inner spacers providing structural guidance and the high-k layers providing electrical isolation, thereby achieving uniformity in the overall gate dielectric structure despite the complex three-dimensional geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves electrical properties by reducing leakage current and enhancing performance, effectively addressing the scaling challenges faced in semiconductor devices.
Implementation Method 1
a high-k dielectric layer that surrounds the inner electrode of the gate electrode
Data Source
AI summary
A semiconductor device comprises a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern on the channel pattern, a gate electrode on the channel pattern, and a gate dielectric layer between the channel pattern and the gate electrode. The gate electrode includes an inner electrode between neighboring first and second semiconductor patterns. The gate dielectric layer includes a high-k dielectric layer that surrounds the inner electrode of the gate electrode and an inner spacer on the high-k dielectric layer. The inner spacer includes a first horizontal part between the high-k dielectric layer and the second semiconductor pattern, a first vertical part between the high-k dielectric layer and the source/drain pattern, and a first corner part that connects the first horizontal part to the first vertical part.