3D-Stacked Gate Structure With Inner Spacer for Dual Work-Function Metals
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Solution Overview
Problem
The challenge in forming two different work-function metal layers for lower and upper nanosheet transistors in a multi-stack semiconductor device, particularly in creating a complementary-metal-oxide semiconductor (CMOS) structure with different threshold voltages for p-type and n-type field-effect transistors, is not effectively addressed by existing methods.
Innovation Solution
A multi-stack semiconductor device is designed with an inner spacer protecting the lower work-function metal layer, allowing for the formation of distinct work-function metal layers by removing the 1st gate metal and work-function metal between upper channel layers, forming an inner spacer, and then adding a 2nd work-function metal layer with different material properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two different work-function metal layers are formed for lower and upper nanosheet transistors to create CMOS structure with different threshold voltages, then the device functionality and threshold voltage differentiation are improved, but the manufacturing complexity and process difficulty increase significantly
Solution Approach 1:
The gate structure is segmented into distinct lower and upper work-function metal layers (first and second work-function metal layers) with different materials or material compositions. This segmentation allows independent control of threshold voltages for lower and upper nanosheet transistors, enabling CMOS functionality while maintaining a systematic manufacturing approach through separate formation processes for each layer.
Solution Approach 2:
Different work-function metal materials or material compositions are applied to specific regions (lower vs. upper gate structures) to achieve locally optimized threshold voltages. The first work-function metal layer is formed for the lower gate structure while the second work-function metal layer is formed for the upper gate structure, allowing each region to have tailored electrical characteristics suitable for its intended function (n-type or p-type transistor).
2Adaptability or versatility
If work-function metal layers are formed differently for lower and upper gate structures, then threshold voltage control is improved, but the manufacturing precision and process control become more challenging
Solution Approach 1:
The first work-function metal layer is formed on the lower gate dielectric layer before forming the upper gate structure components. This preliminary action establishes a stable foundation and allows subsequent processes to build upon it systematically. The sequential formation approach (first lower work-function metal layer, then upper gate dielectric and second work-function metal layer) enables better process control and reduces variability.
Solution Approach 2:
The solution transitions from attempting to differentiate gate structures in the same plane to utilizing the vertical dimension by stacking lower and upper nanosheet transistors with their respective work-function metal layers at different heights. This dimensional approach allows independent material selection and process optimization for each layer without interfering with the other, thereby improving manufacturing precision while maintaining threshold voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the differentiation of threshold voltages for lower and upper nanosheet transistors, facilitating the formation of CMOS structures with improved reliability and connectivity in the multi-stack semiconductor device.
Implementation Method 1
an inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure
Implementation Method 2
a gate structure surrounding all surfaces of the nanosheet channel layers
Implementation Method 3
lower and upper work-function metal layers of the gate structure may be formed to include different materials or material compounds to have different threshold voltages
Data Source
AI summary
Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.