Stacked Gate Isolation Structures for Leakage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing device density and reducing short channel effects and leakage current as it scales down, particularly due to high aspect ratios between adjacent spacers in stacked semiconductor devices, which lead to cross-talk and fabrication difficulties.
Innovation Solution
The implementation of stacked gate structures with nanostructures such as nanowires and nanosheets, along with multi-step gate formation processes and selective release of nanostructures, provides improved isolation and channel quality by forming gate isolation structures between vertically-stacked gate structures, enabling better device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then productivity is improved, but short channel effects and source/drain tunneling increase causing leakage current and device failure
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional stacked transistors with vertical channel orientation. This dimensional change allows continued scaling of lateral dimensions while maintaining channel length through vertical stacking, thereby improving integration density without exacerbating short channel effects that plague planar structures.
Solution Approach 2:
The patent implements nested gate structures where gate electrodes wrap around vertical channels in a concentric arrangement. The gate structure is nested around the channel region, with control gates positioned at multiple levels (first and second gates at different heights), creating a gate-all-around configuration that provides enhanced electrostatic control while enabling three-dimensional integration.
2Productivity
If device dimensions are scaled down to increase storage capacity, then productivity is improved, but leakage current increases due to short channel effects
Solution Approach 1:
By stacking transistors vertically and orienting channels in the vertical direction, the patent achieves higher storage capacity through three-dimensional integration rather than lateral scaling. This approach maintains effective channel length while increasing density, thereby improving storage capacity without the leakage current problems associated with reduced lateral dimensions.
Solution Approach 2:
The patent employs composite material structures including alternating semiconductor layers with different germanium concentrations (first and second semiconductor layers having different germanium atomic concentrations) to form the channel region. These composite materials provide tailored electrical properties that reduce leakage current while maintaining high carrier mobility, addressing the leakage issue without sacrificing performance.
3Reliability
If stacked gate structures are implemented to improve isolation and reduce leakage, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial gate structures and isolation structures before final gate formation. The process includes forming first and second gate structures, selectively removing portions, and forming additional isolation structures in advance. These preliminary steps establish the foundation for subsequent gate formation steps, enabling complex stacked configurations through systematic progression rather than simultaneous complexity.
Solution Approach 2:
The patent uses intermediary structures including sacrificial gate structures, isolation structures, and semiconductor layers with different germanium concentrations as mediators during fabrication. These intermediary elements facilitate the formation of final gate structures by providing etch selectivity, mechanical support, and process control. The sacrificial gate structures serve as temporary placeholders that are removed after defining the final gate geometry, simplifying the overall manufacturing process despite the multi-step nature of the fabrication.
Data Source
AI summary
The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.