Stacked NMOS/PMOS Gate Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scale-down of MOSFETs in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric characteristics and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with active regions and a field region, where channel patterns are stacked and a gate electrode extends across the field region with a decreasing lower portion width from the substrate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MOSFETs are scaled down to meet increasing demand for small pattern size, then layout footprint is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertically stacked channel patterns. Multiple channel patterns are stacked in the vertical direction to increase the effective channel width and drive current capability without increasing the lateral layout footprint, thereby maintaining small device area while improving operational properties through enhanced current drive and transistor performance
Solution Approach 2:
The patent implements nested structures where gate electrodes wrap around vertically stacked channel patterns in a multi-layer configuration. The gate electrode structure encompasses the channel patterns from multiple sides, creating a surround-gate effect that enhances electrostatic control and improves device performance without increasing the lateral footprint
2Reliability
If gate electrode lower portion width is decreased to improve insulating properties, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode is designed with non-uniform cross-sectional dimensions, where the lower portion (near the substrate) has a smaller width compared to the upper portion. This local variation in geometry provides enhanced insulating properties and electrical isolation at the critical substrate interface region, while the upper wider portion facilitates better connectivity and reduced resistance. The localized dimensional optimization improves reliability without requiring ultra-precise control across the entire gate structure
Solution Approach 2:
The patent employs parameter changes in the gate electrode geometry, specifically varying the width parameter along the vertical axis. The lower portion width is optimized to provide adequate insulation, while the upper portion width is increased to maintain electrical performance. This gradual parameter transition allows for improved insulating properties while maintaining manufacturability through standard fabrication processes
Data Source
AI summary
A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.