Stacked Gate-Line Layout for Narrow-Bezel Display Panels
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Solution Overview
Problem
Current display devices have a significant non-display area, known as the bezel area, which limits their size reduction and weight minimization due to the presence of unnecessary conductive patterns and fan-out lines.
Innovation Solution
The display device design incorporates a novel arrangement of conductive patterns and transistors that bypasses the need for separate fan-out lines by using contact holes to connect gate lines and upper electrodes, allowing for a reduced non-display area by integrating additional lines and patterns within the conductive patterns, thereby minimizing the bezel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If separate fan-out lines and conductive patterns are used to connect gate lines and upper electrodes, then electrical connectivity is ensured, but the non-display area (bezel area) increases
Solution Approach 1:
The patent merges the fan-out lines with the gate lines by making them coincide in space. The gate lines serve dual functions: as gate electrodes for transistors and as fan-out lines for electrical connection. This integration eliminates separate conductive patterns, reducing the non-display area while maintaining necessary electrical connectivity between the active pattern and upper electrodes.
2Area of stationary object
If the display area is enlarged to reduce device size, then the non-display area decreases, but routing complexity for connection lines increases
Solution Approach 1:
The patent resolves routing complexity by transitioning from planar routing to three-dimensional stacking. Multiple connection lines (gate lines, data lines, control lines) are routed in different vertical layers rather than spreading horizontally across the display area. This allows the display area to be maximized while connection lines are organized in the vertical dimension, eliminating routing conflicts.
3Reliability
If separate conductive patterns are added for fan-out connections, then electrical connectivity is improved, but device weight increases
Solution Approach 1:
The gate lines are designed to perform multiple functions simultaneously: serving as gate electrodes for transistor operation and as fan-out lines for electrical connection to upper electrodes. This multi-functionality eliminates the need for separate dedicated fan-out conductive patterns, reducing overall material usage and device weight while maintaining reliable electrical connectivity.
Data Source
AI summary
A display device includes a first active pattern, a first conductive pattern including a gate electrode overlapping the first active pattern, a first gate line overlapping the first active pattern and extending in a first direction, and a second gate line extending in the first direction, a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction, a second active pattern disposed on the second conductive pattern and including a material different from a material of the first active pattern, and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping the third gate line and connected to the third gate line, and a second upper electrode overlapping the fourth gate line and connected to the fourth gate line.