Stacked Gate Electrode Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing parasitic capacitance due to the thickness of gate electrode structures, which affects the electrical characteristics of transistors in peripheral circuits.
Innovation Solution
The semiconductor device design includes a substrate with active regions and isolation regions, where the gate electrode structures are formed with polysilicon and metal patterns stacked sequentially, with the upper surface of the isolation layer pattern being higher than the polysilicon patterns, reducing the vertical thickness of the polysilicon patterns and thus decreasing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode structure is formed with conventional thickness, then the transistor can be manufactured with standard processes, but the parasitic capacitance increases affecting electrical characteristics
Solution Approach 1:
The patent transitions from a conventional planar gate electrode to a three-dimensional stacked structure consisting of multiple polysilicon layers and metal layers. This vertical stacking in the thickness dimension reduces the horizontal footprint while maintaining electrical function, thereby reducing parasitic capacitance between the gate and surrounding structures.
Solution Approach 2:
The gate electrode structure employs a composite construction with alternating layers of polysilicon and metal materials. This composite structure optimizes both electrical conductivity and capacitance characteristics, where the metal layers provide high conductivity while the polysilicon layers contribute to the overall capacitance reduction through their thinner profile and different dielectric properties.
2Object-affected harmful factors
If the polysilicon pattern thickness is reduced to decrease parasitic capacitance, then the electrical characteristics improve, but the gate electrode structure becomes more difficult to manufacture with standard thickness tolerances
Solution Approach 1:
The gate electrode is divided into multiple discrete layers (first polysilicon layer, first metal layer, second polysilicon layer, second metal layer) stacked sequentially. Each layer can be manufactured with standard thickness tolerances independently, and the cumulative effect of these thin layers achieves the overall capacitance reduction without requiring any single layer to be manufactured with excessive precision.
Solution Approach 2:
The patent changes the thickness parameter of individual polysilicon layers to be thinner than conventional single-layer gates, while compensating for the total gate thickness through the addition of metal layers. This parameter optimization reduces the dielectric thickness between gate and channel, thereby reducing parasitic capacitance while maintaining manufacturability through standard process capabilities.
Data Source
AI summary
A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.