Stacked Gate Mold Structure for High-Integration Memory Holes
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Solution Overview
Problem
The increasing demand for improved price competitiveness of semiconductor devices necessitates enhanced integration levels, which is hindered by interference between data storage regions and stacked gates.
Innovation Solution
A method of forming a semiconductor device involves creating a mold structure with alternately stacked interlayer insulating layers and gate layers of different etch selectivity materials, forming extended holes with recessed regions, and constructing memory vertical structures within these holes to reduce interference and increase integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stacking number of gates is increased to improve degree of integration, then the degree of integration is improved, but interference between data storage regions opposing the gates is increased
Solution Approach 1:
The patent transitions from planar gate structures to vertically stacked gate structures, moving the integration approach into the third dimension. Multiple gates are stacked perpendicular to the substrate surface, allowing increased integration density without expanding the lateral footprint. This dimensional change enables more data storage regions to be packed into the same area while maintaining reduced interference through proper vertical spacing and isolation structures.
Solution Approach 2:
The patent divides the gate structure into multiple discrete stacked gates, each separated by interlayer insulating layers. This segmentation allows independent control and spacing of each gate, reducing electromagnetic interference between adjacent data storage regions while maintaining high integration. The segmented structure enables precise positioning and isolation of each gate layer.
2Manufacturing precision
If etching processes are performed to form extended holes with recessed regions, then manufacturing precision is improved, but process complexity is increased
Solution Approach 1:
The patent applies local quality by using different etching conditions for different regions of the gate structure. The etching process is optimized to create recessed regions at specific locations (at the gate interfaces with interlayer insulating layers) while maintaining uniform depth and shape control. This localized precision etching achieves high manufacturing precision for the extended holes without requiring uniformly complex processes across the entire structure.
Solution Approach 2:
The patent utilizes parameter changes in the etching process, such as adjusting etchant composition, temperature, and exposure time, to achieve the desired extended hole geometry with recessed regions. By optimizing these parameters, the process achieves high precision in forming the complex hole shapes while managing overall process complexity through controlled variable adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the degree of integration by minimizing interference between data storage regions and gate structures, thereby improving the performance and efficiency of semiconductor devices.
Implementation Method 1
the second layer including a second material having an etch selectivity different from an etch selectivity of the first material; forming the hole as an extended hole, the forming the hole as the extended hole including forming recessed regions by partially etching the gate layers, exposed by the hole, by performing an etching process in which an etching speed of the second material is different from an etching speed of the first material
Data Source
AI summary
A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.