Stacked-Gate Super-Junction MOSFET Termination Design
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Solution Overview
Problem
Existing super-junction MOSFET construction technologies face limitations in device pitch, leading to wasted semiconductor volume, larger device sizes, and reduced reliability and yield due to termination difficulties.
Innovation Solution
A stacked-gate super-junction MOSFET design with a conductive semiconductor substrate featuring lightly-doped or intrinsic epitaxial layers, vertical trenches forming intermediate mesas, and a novel termination structure that includes a termination well and electric field barrier to enhance charge compensation and control the channel between mesa tops and sidewall layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional super-junction construction is used, then charge compensation structure is formed, but device pitch is limited causing semiconductor volume waste
Solution Approach 1:
The patent transitions from planar device architecture to a three-dimensional stacked-gate configuration. Multiple gate structures are stacked vertically above the channel, enabling charge compensation structures to be formed in the vertical dimension rather than being constrained by lateral pitch. This dimensional transition allows fuller utilization of the semiconductor volume while maintaining effective charge compensation.
Solution Approach 2:
The device is divided into multiple discrete gate structures stacked vertically, with each gate contributing to the overall charge compensation. This segmentation of the gate function into multiple stacked elements allows the charge compensation structure to extend through the vertical dimension, improving volume utilization without being limited by lateral device pitch.
2Reliability
If traditional super-junction construction is used, then charge compensation structure is formed, but termination difficulty increases reducing reliability and yield
Solution Approach 1:
By moving the charge compensation function to the vertical dimension through stacked gates, the lateral termination requirements are relaxed. The termination structure can now extend vertically rather than requiring complex lateral termination at device edges, significantly easing manufacturing and improving reliability.
Solution Approach 2:
The stacked-gate structure is designed to extend the charge compensation region vertically before termination is required. This preliminary extension of the compensation structure into the vertical dimension prepares the device for easier termination by reducing the lateral distance to termination points, thereby improving yield and reliability.
3Reliability
If on-state resistance is minimized, then current conduction is improved, but breakdown voltage decreases
Solution Approach 1:
The stacked-gate configuration distributes the voltage blocking function across multiple vertically-stacked gate structures. Each gate contributes to the overall breakdown voltage capability, allowing the device to achieve high breakdown voltage while maintaining low on-state resistance through the combined effect of multiple gates in series vertically.
Solution Approach 2:
The device employs a composite structure with alternating n-type and p-type doped regions forming the stacked gates and charge compensation structures. This composite doping arrangement creates multiple depletion regions that collectively provide high breakdown voltage while the heavily-doped contact regions maintain low on-state resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a compact form factor for high-current, moderate to high-voltage applications with improved reliability and yield by minimizing on-state resistance and maximizing breakdown voltage, while addressing the challenges of device size and termination issues.
Implementation Method 1
diffusing the dopant atoms into the bulk of the one or more mesas
Data Source
AI summary
A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.