Stacked Gate Electrode Structure for Dense Nanosheet Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently processing and manufacturing increasingly complex and smaller semiconductor integrated circuits (ICs), which requires improved manufacturing techniques to maintain efficiency and reduce costs.
Innovation Solution
The described method involves forming a stack of semiconductor layers over a substrate, using alternating layers of different etch selectivity and oxidation rates, and employing various patterning and etching processes to create nanosheet channels and gate electrode layers, with the use of dielectric features and conductive layers to separate and connect gate electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent divides the gate electrode structure into multiple discrete layers (first gate electrode layer, second gate electrode layer, third gate electrode layer) separated by dielectric features. This segmentation allows each layer to be formed and processed independently, simplifying the manufacturing process while achieving the desired complex 3D structure for high-density integration.
Solution Approach 2:
The patent transitions from planar 2D transistor structures to three-dimensional vertically-stacked gate electrode structures. By adding the vertical dimension with multiple stacked gate layers, the device achieves higher functional density without proportionally increasing processing complexity, as the stacking approach can be implemented using established deposition and etching techniques.
2Quantity of substance
If functional density is increased with smaller geometry sizes, then more circuits fit per chip area, but manufacturing complexity increases
Solution Approach 1:
The gate electrode is segmented into multiple discrete layers that can be formed using separate deposition and patterning steps. Each layer is defined by its own mask and etch process, allowing for precise control and independent optimization of each gate layer, which simplifies the overall manufacturing of high-density multi-layer structures.
Solution Approach 2:
The patent implements a nested structure where multiple gate electrode layers are vertically stacked and interconnected through conductive layers that pass through dielectric features. This nesting approach allows multiple functional elements to be integrated in the vertical dimension, increasing circuit density while using standard semiconductor fabrication techniques.
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.