Stacked Gate Semiconductor Structure With Plasma-Free Isolation
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Solution Overview
Problem
Existing methods for integrating vertically stacked transistors in logic chips face challenges such as high deposition temperatures, plasma damage to organic self-aligned monolayers, and complex etch-stop layer incorporation, which hinder efficient production of complementary FET devices.
Innovation Solution
A plasma-free deposition process at low temperatures is used to form isolation dielectrics between vertically stacked semiconductor devices, combined with selective deposition of work function metals and high-k dielectrics, enabling monolithic integration of complementary FET devices with split and common gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma-based deposition is used to form isolation dielectrics, then deposition speed and film quality can be improved, but organic self-aligned monolayers are damaged by plasma exposure
Solution Approach 1:
The harmful plasma component is extracted and removed from the deposition process. The patent employs plasma-free atomic layer deposition (ALD) to form isolation dielectrics, eliminating plasma exposure that damages organic self-aligned monolayers while maintaining the benefits of high-quality dielectric film formation through sequential chemical reactions.
Solution Approach 2:
An intermediary plasma-free chemical vapor deposition process is introduced as a mediator between the organic monolayer and the isolation dielectric formation. This intermediary ALD process uses precursors that react chemically without plasma activation, protecting the organic monolayer from damage while enabling dielectric deposition.
2Manufacturing precision
If high deposition temperatures are used to form isolation dielectrics, then film density and quality can be improved, but processing complexity and cost increase
Solution Approach 1:
The deposition temperature parameter is changed from conventional high temperatures to low temperatures by using plasma-free ALD processes. This parameter change enables isolation dielectric formation at temperatures compatible with organic monolayers while maintaining film quality through controlled chemical reactions and multiple deposition cycles.
3Reliability
If complex etch-stop layer incorporation is used to separate stacked devices, then device isolation can be improved, but manufacturing complexity and time increase
Solution Approach 1:
The complex multi-layer etch-stop structure is extracted and replaced with a simplified single-layer isolation dielectric approach. The patent forms isolation dielectrics directly at the interface between stacked devices using plasma-free ALD, eliminating the need for separate etch-stop layer deposition, patterning, and etching steps.
Solution Approach 2:
The isolation function and the dielectric formation function are merged into a single plasma-free ALD process step. By combining these functions, the patent eliminates multiple sequential steps including etch-stop layer formation, pattern transfer, and selective etching, thereby simplifying the manufacturing process and increasing productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for rapid implementation of stacked transistors, reducing production costs and time-to-market, and facilitates high-volume manufacturing of complementary FET technology by 2028, addressing scaling and isolation challenges in vertically stacked transistors.
Implementation Method 1
a plasma-free deposition process at low temperatures is used to form isolation dielectrics between vertically stacked semiconductor devices
Implementation Method 2
The monolayer can include a self-assembled monolayer (SAM), and depositing the monolayer includes depositing the SAM on the uncovered dielectric surfaces
Data Source
AI summary
Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.