Vertically Stacked Gate Electrodes With Segmented Isolation
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Solution Overview
Problem
The integration of semiconductor elements in devices has decreased despite the need for higher data processing capacity, necessitating improved three-dimensional transistor structures to enhance semiconductor device reliability.
Innovation Solution
A semiconductor device design featuring vertically stacked gate electrodes, isolation regions, and auxiliary isolation regions to support the gate electrode stack, ensuring reliable data processing and storage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked gate electrodes are used to increase integration, then device capacity increases, but structural complexity and reliability risks increase
Solution Approach 1:
The gate electrode stack is segmented into multiple individual gate electrodes (first gate electrode, second gate electrode, third gate electrode) stacked vertically. Each gate electrode can be independently controlled, allowing for complex device functionality while maintaining manageable structural complexity through modular design.
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional vertically stacked gate electrode structures. This dimensional change increases integration density by utilizing the vertical space above the substrate, allowing more gate electrodes to be packed into a smaller footprint area.
2Quantity of substance
If vertically stacked gate electrodes are used to increase integration, then device capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
A support structure is formed on the substrate before the gate electrodes are stacked. This preliminary action provides a stable foundation and alignment reference that facilitates the subsequent formation of vertically stacked gate electrodes with precise positioning, reducing manufacturing precision requirements.
Solution Approach 2:
The support structure acts as an intermediary element between the substrate and the stacked gate electrodes. It provides mechanical support and alignment guidance, mediating the complex alignment requirements and enabling precise positioning of multiple gate electrodes during manufacturing.
3Reliability
If isolation regions penetrate through the gate electrode stack, then device performance improves, but structural stability may be compromised
Solution Approach 1:
The isolation structure is segmented into multiple parts: a support structure at the bottom providing mechanical strength, and multiple isolation regions (first, second, third isolation regions) stacked above it. This segmentation allows the lower portion to provide structural support while the upper portions provide electrical isolation, resolving the contradiction between performance and stability.
Solution Approach 2:
Different portions of the isolation structure have different properties: the support structure has high mechanical strength to maintain structural integrity, while the isolation regions have high electrical insulation properties to improve device performance. This local differentiation of properties allows both requirements to be satisfied simultaneously.
Data Source
AI summary
A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction.