Stacked Gate Semiconductor Apparatus Routing Congestion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase the density of semiconductor devices while managing the complexity and scaling down of semiconductor devices to smaller sub-micron sizes, which requires improved structures and methods for processing and manufacturing.
Innovation Solution
The method involves forming three-dimensional complementary field-effect transistors (FETs) by stacking n-type and p-type FETs vertically, with staggered or stair-cased source and drain electrodes, and using dielectric materials to separate and isolate the gates, allowing for efficient area scaling and reduced routing congestion by bypassing gates with conductive traces and using common routing tracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to smaller sub-micron sizes to increase density, then production efficiency and cost are improved, but processing and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional device layout to three-dimensional vertical stacking of FETs. Multiple FETs are stacked along the vertical direction (perpendicular to substrate), allowing higher device density without further lateral scaling. This dimensional change enables continued productivity improvement while avoiding the processing complexity associated with sub-micron planar scaling.
Solution Approach 2:
The patent segments the semiconductor device structure into multiple discrete FET units that can be stacked vertically. Each FET in the stack is a separate functional unit with its own gate, channel, and source/drain regions, allowing independent control and simplified manufacturing processes compared to monolithic planar structures.
2Area of stationary object
If three-dimensional stacked FETs are formed to increase device density, then area scaling is achieved, but routing and interconnection complexity increases
Solution Approach 1:
The patent implements common routing tracks that serve multiple stacked FETs simultaneously. A single routing track can connect to source/drain electrodes of multiple FETs in the stack, reducing the total number of routing lines needed compared to dedicated routing for each FET. This multi-functional routing approach reduces interconnection complexity while maintaining area scaling benefits.
Solution Approach 2:
The patent merges multiple routing functions into shared routing infrastructure. Common routing tracks and conductive traces are used to interconnect multiple FETs, consolidating what would otherwise require separate routing paths. This merging reduces routing congestion and simplifies the interconnection network in three-dimensional stacked architectures.
3Area of stationary object
If vertical stacking of FETs is implemented to reduce area, then device density increases, but metallization and interconnection requirements increase
Solution Approach 1:
The patent designs metallization structures that serve multiple functions: conductive traces not only provide electrical connections but also act as inter-layer vias and routing elements. Shared routing tracks serve multiple FETs, reducing the total quantity of metallization material required compared to dedicated interconnections for each stacked FET.
Solution Approach 2:
The patent implements nested interconnection structures where conductive traces and routing tracks are integrated within the three-dimensional FET stack architecture. Metallization is nested within and between FET layers, utilizing vertical and horizontal space efficiently to minimize material requirements while maintaining electrical connectivity.
Data Source
AI summary
Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.