Stacked Gate Electrode Silicide Formation for Flash Memory
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Solution Overview
Problem
In flash memories with high integration, the increasing resistance of control gates due to smaller feature sizes leads to issues like RC delay and voltage drop, and the formation of voids and profile deterioration in metal silicide layers, especially for narrow line widths.
Innovation Solution
A method for forming a gate electrode in semiconductor devices that involves stacking tunnel dielectric, silicon, intergate dielectric, and hard mask layers, followed by forming a metal silicide layer through thermal treatment, while using chemical mechanical polishing and selective epitaxial growth to prevent voids and ensure uniformity in the interlayer dielectric and metal silicide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick metal silicide layer is formed to reduce resistance for narrow line widths, then resistance decreases, but voids are formed within the control gate and silicide profile deteriorates
Solution Approach 1:
The control gate is divided into multiple segments: a bottom metal silicide layer formed first, followed by a polysilicon layer, and then a top metal silicide layer. This segmentation allows each layer to be optimized independently - the bottom silicide provides low resistance contact, the polysilicon provides structural integrity, and the top silicide provides uniform coverage without voids.
Solution Approach 2:
The bottom metal silicide layer is formed in advance before the polysilicon layer is deposited. This preliminary action ensures that the low-resistance contact is established first, and subsequent layers are built upon this foundation, preventing void formation while maintaining uniform profile.
2Manufacturing precision
If chemical mechanical polishing is used to form the interlayer dielectric layer, then voids are prevented and uniformity is improved, but the process complexity increases
Solution Approach 1:
The mask pattern serves as an intermediary element that enables the chemical mechanical polishing process. The mask pattern provides a planar reference surface that allows CMP to effectively remove excess interlayer dielectric material and fill narrow spaces uniformly, achieving void-free formation while maintaining process control.
3Productivity
If the feature size of the control gate is decreased for high integration, then integration density increases, but resistance increases causing RC delay and voltage drop
Solution Approach 1:
The control gate uses a composite structure combining metal silicide and polysilicon materials. The metal silicide provides low resistance for high integration density, while the polysilicon provides structural stability. This composite approach maintains low resistance even as feature sizes decrease, preventing RC delay and voltage drop while enabling high integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the formation of a control gate with a uniform metal silicide layer without voids, preventing pitting in the semiconductor substrate and ensuring consistent resistance, thus addressing the challenges of RC delay and voltage drop.
Implementation Method 1
a metal layer is formed on a polysilicon layer and thermally treated to form a metal silicide layer
Implementation Method 2
performing chemical mechanical polishing (CMP) on the deposited dielectric material
Implementation Method 3
growing epitaxial silicon on the second silicon layer by selective epitaxial growth (SEG)
Data Source
AI summary
A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.