Stacked Gate Spacer Formation for Mixed-Voltage Semiconductor Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of high-voltage and low-voltage devices on the same semiconductor chip poses manufacturing challenges due to differing requirements for gate spacer widths, which existing semiconductor structures fail to fully address.
Innovation Solution
A method for forming semiconductor structures with stacked spacers of varying widths by sequentially depositing dielectric layers and using them as etching masks to create spacers with specific widths on high-voltage and low-voltage regions, allowing for the integration of both types of devices without additional process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single gate spacer width is used for both high-voltage and low-voltage devices, then the manufacturing process is simplified, but the performance requirements of high-voltage devices cannot be met
Solution Approach 1:
The patent applies local quality by creating different gate spacer widths in different regions of the semiconductor device. The first gate spacer has a first width for low-voltage devices while the second gate spacer has a second width for high-voltage devices, allowing each region to have the specific quality needed for its function.
Solution Approach 2:
The gate spacer structure is segmented into multiple parts with different widths. The patent divides the gate spacer into a first gate spacer and a second gate spacer, each with different widths tailored to specific device regions, enabling simultaneous satisfaction of different voltage requirements.
2Reliability
If different gate spacer widths are formed for high-voltage and low-voltage devices, then device performance requirements are met, but manufacturing complexity increases
Solution Approach 1:
The patent employs universality by using a single set of dielectric layers (first, second, and third dielectric layers) to serve multiple functions: they form both the first and second gate spacers with different widths, and they serve as etching masks for each other during the fabrication process.
Solution Approach 2:
The patent merges multiple functions into a unified structure. The stacked dielectric layers are formed in a sequence where each layer serves as both a structural component and an etching mask, combining the functions of spacer formation and pattern definition into a single integrated process.
3Ease of manufacture
If conventional single-layer spacer structures are used, then manufacturing is simpler, but precise control of spacer width for different device types is not achieved
Solution Approach 1:
The patent transitions from a single-dimensional spacer structure to a multi-dimensional stacked structure. By adding vertical layering with multiple dielectric layers of different thicknesses, the system achieves precise width control in the horizontal dimension while maintaining manufacturing simplicity through sequential deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the accurate formation of spacers with predetermined widths, improving the breakdown voltage and reducing manufacturing complexities, while maintaining the reliability of the semiconductor structure.
Implementation Method 1
The third dielectric layer is patterned to form a first portion of the third dielectric layer and a second portion of the third dielectric layer in the first region and the second region, respectively. The second portion is covered and the first portion of the third dielectric layer is partially removed to form a first etching mask.
Implementation Method 2
The second dielectric layer is patterned by using the first etching mask and the second portion of the third dielectric layer as a second etching mask, to expose a portion of the first dielectric layer.
Implementation Method 3
The portion of the first dielectric layer is removed to form a first stacked spacer and a second stacked spacer on the sidewalls of the first gate structure and the second gate structure, respectively.
Data Source
AI summary
A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.