Stacked Gate Structures With Step Contacts for Lower Capacitance
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Solution Overview
Problem
The integration and operational reliability of semiconductor devices are limited by the area occupied by unit memory cells, especially in three-dimensional stacked structures, leading to increased parasitic capacitance and RC delay.
Innovation Solution
A semiconductor device with stacked gate structures and gap-fill insulating layers is designed, featuring interconnected gate lines and step structures to reduce parasitic capacitance and RC delay, while maintaining electrical connectivity through wiring lines and supports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional stacked structures are used to improve integration, then the degree of integration is improved, but parasitic capacitance and RC delay increase
Solution Approach 1:
The patent divides the contact region into multiple segments by introducing step structures at different heights. The first contact plug connects to the first gate line at a lower level, while the second contact plug connects to the second gate line at a higher level. This segmentation allows each contact plug to be optimally positioned, reducing overlapping areas and thereby reducing parasitic capacitance between gate lines while maintaining high integration through vertical stacking.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked structure by introducing vertical step structures. The step structure creates different height levels (z-dimension) for contact plugs, allowing them to connect to different gate lines at different vertical positions. This dimensional change enables higher integration density while reducing parasitic capacitance through optimized spatial arrangement.
2Reliability
If contact plugs are positioned to connect to gate lines, then electrical connectivity is achieved, but overlapping areas increase parasitic capacitance
Solution Approach 1:
The patent applies local quality by creating different structural configurations in different regions of the contact plug structure. The first contact plug has a different shape and position relative to the first gate line compared to how the second contact plug is positioned relative to the second gate line. This localized optimization minimizes overlapping areas at each connection point, reducing parasitic capacitance while maintaining reliable electrical connectivity for each gate line independently.
3Productivity
If unit memory cell area is reduced to improve integration, then degree of integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a nested structure where step structures are formed within the contact region, and contact plugs are positioned within these step structures. The first step structure and second step structure are nested at different vertical levels, with each containing a respective contact plug. This nested arrangement maximizes space utilization within the unit memory cell area while maintaining clear manufacturing boundaries and alignment references, thereby reducing manufacturing precision requirements despite high integration density.
Data Source
AI summary
A semiconductor device may include: a first gate structure including first gate lines, a first step structure including first pads, a first gap-fill insulating layer located between the first gate lines and the first step structure, and first wiring lines connecting the first gate lines and the first pads, respectively; and a second gate structure including second gate lines located on the first gate lines, a second step structure located on the first gap-fill insulating layer and including second pads, a second gap-fill insulating layer located on the first step structure, and second wiring lines connecting the second gate lines and the second pads, respectively.