Vertically Stacked Gate Structure for Wafer Alignment Accuracy
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Solution Overview
Problem
Current semiconductor device scaling techniques are approaching limits in increasing density and integration, particularly in aligning integrated circuits on lower and upper semiconductor substrates, which hampers performance and integration density.
Innovation Solution
A semiconductor device and fabrication method that enhance alignment accuracy between integrated circuits on lower and upper substrates through specific gate structures, interlayer insulating films, and etch stop layers, allowing for the formation of connection contacts that penetrate the upper substrate, thereby improving integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate transistor scaling is used to increase density, then integration density is improved, but scaling limits are reached that prevent further density increases
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple active patterns are stacked in the vertical direction above a single gate electrode, enabling continued density increase by utilizing the third dimension rather than continuing to scale lateral dimensions which have reached physical limits.
2Quantity of substance
If three-dimensional stacking through wafer bonding is used to increase density, then integration density is improved, but alignment accuracy between lower and upper integrated circuits deteriorates
Solution Approach 1:
Alignment marks are formed on both the lower and upper substrates before the wafer bonding process. These pre-formed marks serve as reference points that guide the alignment process during bonding, ensuring precise registration of corresponding features between stacked layers without requiring complex real-time alignment adjustments.
Solution Approach 2:
The upper integrated circuit pattern is designed as a copy or mirror image of the lower circuit pattern. By replicating the same geometric features and spacing on both substrates, the alignment process becomes simpler as the same alignment marks and feature dimensions are used on both sides, reducing alignment errors.
3Device complexity
If conventional gate structures are used in three-dimensional stacking, then device simplicity is maintained, but connection reliability between stacked substrates deteriorates
Solution Approach 1:
The gate electrode structure uses composite materials with different properties: a first material (e.g., tungsten) for the main gate electrode body providing mechanical strength and electrical conductivity, and a second material (e.g., titanium nitride or tantalum nitride) for the cap layer providing excellent adhesion to the overlying interlayer insulating film and barrier properties. This composite structure ensures reliable connections through the stacked substrates.
Data Source
AI summary
A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.