Stacked Gate Wall Structure for Reliable Scaled Memory Cells
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, there is a need to enhance the reliability of memory cells to improve device performance and reduce production costs while maintaining the advantages of non-volatile memory, such as data retention without power.
Innovation Solution
A manufacturing method for non-volatile memory involving the formation of stacked gate structures and wall structures on a substrate, using multiple dielectric and conductive layers, and specific process steps like ion implantation and chemical vapor deposition to define active areas and pattern conductive layers, ensuring uniformity and reliability of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the dimensions of memory devices are reduced to increase integration level, then device size is reduced, but reliability of memory cells deteriorates
Solution Approach 1:
The gate structure is segmented into multiple stacked gates (first stacked gate and second stacked gate) separated by an inter-gate dielectric layer. This segmentation allows each gate to be independently formed and controlled, improving reliability while maintaining reduced device dimensions. The segmentation enables better electrical isolation and control over charge storage regions.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional stacked gate structures. By stacking gates vertically rather than arranging them horizontally, the device achieves higher integration density without proportionally reducing individual cell dimensions, thereby maintaining reliability while reducing overall device footprint.
2Reliability
If multiple stacked gate structures are formed to improve reliability, then manufacturing complexity increases, but device performance improves
Solution Approach 1:
The inter-gate dielectric layer is formed between the first and second stacked gates during the fabrication process. This preliminary formation of the dielectric layer simplifies subsequent processing by providing a pre-established isolation structure, reducing the need for additional complex steps to create electrical isolation between stacked gates.
Solution Approach 2:
The stacked gate structures serve multiple functions: they provide electrical control over the memory cell, create charge storage regions, and enable independent operation of multiple gates. This multi-functionality reduces the need for separate structures, simplifying the overall device architecture despite the increased stacking complexity.
3Volume of moving object
If device dimensions are reduced, then integration level increases, but production cost control becomes more difficult
Solution Approach 1:
Multiple functional layers (tunnel dielectric, charge trap dielectric, blocking dielectric) are merged into a single stacked gate structure. This consolidation reduces the number of separate fabrication steps and material depositions required, lowering production costs while achieving the necessary functionality in a compact dimension.
Solution Approach 2:
The patent utilizes changes in dielectric material properties and layer thicknesses to optimize device performance at reduced dimensions. By carefully controlling parameters such as dielectric constant, layer thickness, and doping concentrations, the device maintains reliability and performance while minimizing size, making manufacturing more cost-effective.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability and performance of memory cells, allowing for smaller device dimensions with improved integration and reduced production costs, while maintaining data retention capabilities.
Implementation Method 1
specific process steps like ion implantation and chemical vapor deposition to define active areas and pattern conductive layers
Implementation Method 2
specific process steps like ion implantation and chemical vapor deposition to define active areas and pattern conductive layers
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.