Stacked Gate Semiconductor Layout for Shorter Gate Wiring
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving higher performance and integration density, with limitations in design flexibility and electrical characteristics.
Innovation Solution
A semiconductor device design featuring a first and second lower gate structure, an upper device isolation structure, and contact plugs extending through the isolation structure to connect gate structures, enhancing electrical connectivity and reducing wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor device structures are used, then manufacturing processes are simpler, but integration density and electrical characteristics are limited
Solution Approach 1:
The patent implements a three-dimensional stacked gate structure with lower and upper gate structures positioned at different vertical levels. This dimensional transition from planar to vertical architecture enables higher integration density by utilizing the third dimension (depth) for additional transistor stacking, while the modular stacked design maintains manufacturing feasibility through sequential formation processes
2Reliability
If longer wiring is used to connect gate structures, then device layout is more flexible, but electrical resistance and signal delay increase
Solution Approach 1:
The patent merges the lower gate structure and upper gate structure into a unified stacked configuration where both gates are vertically aligned and closely integrated. This merging reduces the horizontal wiring distance between gate connections by utilizing vertical stacking, thereby decreasing electrical resistance and signal delay while maintaining design flexibility through the compact three-dimensional arrangement
3Productivity
If planar device layout is used, then manufacturing is easier, but performance and integration density are constrained
Solution Approach 1:
The patent segments the transistor structure into distinct lower and upper gate components stacked vertically, with separate active regions and isolation structures at different levels. This segmentation enables independent optimization and formation of each layer through sequential manufacturing steps, making the complex three-dimensional structure manufacturable while achieving enhanced performance and integration density
Data Source
AI summary
Some example embodiments provide a semiconductor device comprising a first lower gate structure extending in a first direction, an upper device isolation structure extending from the first lower gate structure in the first direction, a second lower gate structure spaced apart from the first lower gate structure in a second direction, the second direction intersecting the first direction, and the second lower gate structure extending in the first direction, an upper gate structure extending from the second lower gate structure in the first direction, a lower active region extending in the second direction and extending through the first lower gate structure, an upper active region extending in the second direction and extending through the upper gate structure, and a first contact plug extending through the upper device isolation structure in a third direction, and the first contact plug contacting the first lower gate structure.