Stacked Electrostatic Gates for Wider-Pitch Quantum Dot Control

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Solution Overview

Problem

Existing solutions for electrostatic control gates in quantum devices require a higher density of gate production, leading to complications due to the need for gate pitches between 40 nm and 60 nm, making their production challenging.

Innovation Solution

A device with two-stage electrostatic control gates, where the first and second gates are superimposed, allowing independent adjustment of their potentials, enabling a larger pitch and simplifying production by reducing the density of gate production requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If electrostatic control grids are manufactured with high density to control quantum dots and tunnel barriers, then control precision is improved, but manufacturing complexity increases due to required gate pitches between 40 nm and 60 nm

Engineering Contradiction:

Improvegate pitch precisionVSAvoidgrid fabrication ease

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The control function is segmented into two independent grids: a first grid for controlling quantum dot minimum potential and a second grid for controlling tunnel barrier height. This segmentation allows each grid to be optimized independently, reducing the need for ultra-fine pitch fabrication while maintaining precise control over both quantum dot and barrier parameters.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-plane grid architecture to a stacked three-dimensional architecture where the second grid is positioned above the first grid. This vertical dimensionality change enables independent control of quantum dots and tunnel barriers without requiring proportional increases in lateral pitch precision, thereby simplifying manufacturing.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Device complexity

If single-layer electrostatic control grids are used, then device structure is simplified, but control capability over both quantum dots and tunnel barriers independently is insufficient

Engineering Contradiction:

Improvegrid structure complexityVSAvoidindependent control capability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The stacked grid structure provides multi-functionality: the first grid primarily controls quantum dot minimum potential while the second grid primarily controls tunnel barrier height. Each grid can be independently adjusted to achieve optimal control over different device parameters, enhancing overall adaptability without proportionally increasing complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for easier production of electrostatic control gates by increasing the pitch to twice that of prior art solutions, reducing production difficulties and enabling more effective control over quantum dots and tunnel barriers in quantum devices.

Implementation Method 1

electrostatic control grids each comprising at least one portion of electrically conductive material... arranged above the first or second regions of the semiconductor portion

Methodology Applied

Scientific EffectElectrostatic field: Electric Field

Data Source

PatentEP4060748B1Device with two levels of stacked electrostatic control gates

Publication Date: 2023.09.06 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

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AI summary

Quantum device (100), comprising: - a portion of semiconductor comprising several first regions (108) of quantum dots each disposed between at least two second regions (110) of tunnel barriers and juxtaposed to the two second regions (110); - first grids each comprising a first conducting portion (112); - second grids each comprising a second conducting portion (116) and a second dielectric (118) disposed between the second conducting portion and the first conducting portion of one of the first grids, such that each of the first grids is disposed between the semiconductor portion and one of the second grids; wherein the first and second grids are disposed above the first regions or above the second regions, the second grids being only located in a vertical extension of the first grids.