Vertically Stacked GIP Circuit for Compact Threshold Stability
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Solution Overview
Problem
The increased area requirement and threshold voltage shift due to deterioration of nMOS transistors with oxide semiconductors in Gate In Panel (GIP) driving units, which are formed of two transistors, are problematic in thin display apparatus.
Innovation Solution
A GIP circuit design where a polycrystalline semiconductor and an oxide semiconductor are used in a vertically stacked structure, with a shared gate electrode, and a gate control signal is applied to counteract the bias voltage effect on the oxide semiconductor transistor, thereby preventing threshold voltage shift and reducing the overall area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an inverter unit is formed of two transistors (pMOS with polycrystalline semiconductor and nMOS with oxide semiconductor), then the threshold voltage can be adjusted, but the area is increased and the nMOS transistor deteriorates causing threshold voltage shift
Solution Approach 1:
The patent merges two transistors (pMOS and nMOS) into a single integrated structure where they share a common gate electrode and are formed in close proximity on the substrate. This consolidation reduces the overall area occupied by the inverter unit while maintaining the functionality of both transistor types with their respective semiconductor materials.
Solution Approach 2:
The gate electrode serves multiple functions: it controls both the pMOS transistor (through the first semiconductor layer) and the nMOS transistor (through the second semiconductor layer). This multi-functional design allows a single gate structure to perform the control function for two different transistor types, reducing the need for separate gate electrodes and associated area.
2Adaptability or versatility
If an inverter unit is formed of two transistors, then threshold voltage adjustment is possible, but the area is increased
Solution Approach 1:
The patent merges two transistors (pMOS and nMOS) into a single integrated structure where they share a common gate electrode and are formed in close proximity on the substrate. This consolidation reduces the overall area occupied by the inverter unit while maintaining the functionality of both transistor types with their respective semiconductor materials.
Solution Approach 2:
The patent applies different semiconductor materials (polycrystalline semiconductor for pMOS and oxide semiconductor for nMOS) at different local regions (first and second semiconductor layers) to achieve different threshold voltage characteristics. This local differentiation allows threshold voltage adjustment for each transistor type while maintaining a compact overall structure.
3Adaptability or versatility
If nMOS transistor with oxide semiconductor is used, then threshold voltage can be adjusted, but deterioration occurs causing threshold voltage shift
Solution Approach 1:
The patent implements a feedback mechanism where the gate electrode receives a gate control signal that adjusts the threshold voltage of the nMOS transistor based on its operational state. This feedback control compensates for deterioration effects and maintains stable transistor characteristics over time, preventing threshold voltage drift.
Solution Approach 2:
The patent dynamically changes the gate control signal parameter to adjust the threshold voltage of the nMOS transistor. By modifying the electrical parameter (gate voltage) applied to the oxide semiconductor layer, the threshold voltage can be tuned to compensate for deterioration and maintain reliable operation.
Data Source
AI summary
A GIP circuit according to the present invention includes a substrate, a first semiconductor layer on the substrate, a gate electrode over the first semiconductor layer, a second semiconductor layer over the gate electrode, a gate control electrode over the second semiconductor layer, a gate control signal being applied to the gate control electrode, an insulating layer over the gate control electrode, and a first drain electrode, a second drain electrode, a first source electrode, and a second source electrode over the insulating layer.