Stacked GIP Inverter Circuit for Threshold Shift Compensation
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Solution Overview
Problem
The increased area requirement and threshold voltage shift due to deterioration of nMOS transistors with oxide semiconductors in Gate In Panel (GIP) driving units, which are formed of two transistors, pose challenges in thin display apparatus.
Innovation Solution
A GIP circuit design where a polycrystalline semiconductor and an oxide semiconductor are used for the first and second transistors, respectively, with a shared gate electrode and a gate control signal applied to the oxide semiconductor transistor to counteract threshold voltage shifts, reducing the overall area by overlapping the transistors in the same space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two transistors (pMOS and nMOS) are used to form an inverter unit in GIP driving circuit, then the circuit functionality is achieved, but the area is increased and threshold voltage shifts due to nMOS transistor deterioration
Solution Approach 1:
The patent merges two separate transistors (pMOS and nMOS) into a single integrated transistor structure where the semiconductor layer contains both p-type and n-type doped regions. This consolidation reduces the circuit area by eliminating the need for two separate transistor structures while maintaining the inverter unit functionality through the combined action of the doped regions within the single transistor framework
Solution Approach 2:
The patent applies preliminary anti-action by incorporating a gate control electrode that applies a compensation voltage to counteract the threshold voltage shifts caused by nMOS transistor deterioration. This compensation mechanism is built into the transistor structure to prevent the harmful effects of deterioration before they significantly impact circuit performance
2Manufacturing precision
If nMOS transistor with oxide semiconductor is used in inverter unit, then threshold voltage control is improved, but threshold voltage shifts due to transistor deterioration
Solution Approach 1:
The patent implements feedback by using the gate control electrode to monitor and compensate for threshold voltage shifts in the nMOS transistor. The control electrode receives feedback regarding the transistor's electrical characteristics and adjusts the compensation voltage accordingly to maintain stable threshold voltage operation despite deterioration over time
Solution Approach 2:
The gate control electrode provides preliminary anti-action by applying a compensation voltage that counteracts the expected threshold voltage shifts before they significantly degrade circuit performance. This proactive compensation approach maintains threshold voltage stability throughout the transistor's operational lifetime
3Area of stationary object
If polycrystalline semiconductor and oxide semiconductor are used in stacked structure, then area is reduced by overlapping transistors, but device complexity increases
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor layout to a three-dimensional stacked structure by placing the p-type and n-type doped regions vertically within the semiconductor layer. This dimensional change enables area reduction through overlapping transistor footprints while managing complexity through vertical integration rather than horizontal expansion
Data Source
AI summary
A GIP circuit according to the present invention includes a substrate, a first semiconductor layer on the substrate, a gate electrode over the first semiconductor layer, a second semiconductor layer over the gate electrode, a gate control electrode over the second semiconductor layer, a gate control signal being applied to the gate control electrode, an insulating layer over the gate control electrode, and a first drain electrode, a second drain electrode, a first source electrode, and a second source electrode over the insulating layer.