Stacked Half-Bridge Package With Common Conductive Clip
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Solution Overview
Problem
Conventional packaging methods for power transistors in half-bridge configurations result in large form factors and performance degradation due to high parasitic inductance and resistance from long conductive traces on printed circuit boards.
Innovation Solution
A stacked half-bridge package with a common conductive clip that electrically and mechanically connects control and synchronous transistors, reducing parasitic inductance and resistance while maintaining a small footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If control transistor and synchronous transistor are arranged side by side on a PCB substrate, then the package can accommodate both transistors, but the package footprint becomes large and parasitic inductance increases due to long conductive traces
Solution Approach 1:
The patent transitions from a planar PCB layout to a three-dimensional stacked configuration where the control transistor and synchronous transistor are positioned on different layers. This vertical stacking eliminates the need for long lateral trace connections, significantly reducing parasitic inductance while maintaining a compact package footprint.
Solution Approach 2:
The patent implements a nested structure where one transistor is positioned above the other in a stacked configuration, with intermediate connection structures (such as conductive vias or bonded wires) connecting corresponding terminals between layers. This nesting approach minimizes the external package size while keeping interconnection paths short.
2Reliability
If conductive traces are used to connect control transistor and synchronous transistor on PCB, then the transistors can be electrically connected to form half-bridge, but parasitic inductance and resistance increase due to long routing paths
Solution Approach 1:
By stacking transistors vertically on different PCB layers and connecting them through short vertical paths (vias or bonded wires), the patent eliminates long lateral trace routing. This dimensional change reduces both the length and complexity of current paths, minimizing parasitic inductance and resistance.
Solution Approach 2:
The patent introduces intermediate connection structures (conductive vias, bonded wires, or trace segments on intermediate layers) that provide direct electrical pathways between corresponding terminals of stacked transistors. These intermediaries create short, low-impedance connection paths that replace long external traces.
Data Source
AI summary
According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe.