Stacked Vertical Hall IC Layout for Sensitivity and Offset Control
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Solution Overview
Problem
Conventional vertical Hall elements in Hall ICs suffer from low sensitivity and high residual offsets due to finite well depths and lack of ideal four-fold symmetry, limiting their accuracy in direct angle sensor and 3D applications.
Innovation Solution
A Hall integrated circuit is developed using a stacked wafer structure with epitaxial semiconductor layers, where Hall terminals on both surfaces are arranged to achieve four-fold symmetry and optimal sensitivity, with deep trench isolation and through-silicon vias for enhanced electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional vertical Hall elements are used with finite well depths, then manufacturing is simplified, but sensitivity is limited
Solution Approach 1:
The patent transitions from conventional planar Hall elements to a three-dimensional stacked wafer structure. Multiple Hall sensing layers are stacked vertically with alternating conductivity types, enabling the Hall sensing function to extend in the vertical dimension. This dimensional change increases the effective sensing volume and improves sensitivity without requiring excessively deep single wells.
Solution Approach 2:
The patent employs composite semiconductor structures with alternating n-type and p-type conductivity layers. These composite layers are formed through sequential epitaxial growth, creating a multi-layered material system that enhances Hall sensitivity while maintaining manufacturability through standard semiconductor processes.
2Measurement precision
If conventional vertical Hall elements without four-fold symmetry are used, then device complexity is reduced, but residual offsets remain high
Solution Approach 1:
The patent deliberately introduces asymmetric doping patterns within the stacked structure. Specifically, adjacent Hall sensing layers are doped with alternating conductivity types (n-type, p-type, n-type, p-type), creating a controlled asymmetric arrangement that generates opposing Hall voltages. This asymmetric design enables offset cancellation when the layers are combined, reducing residual offsets while maintaining a relatively simple overall device architecture.
3Measurement precision
If epitaxial semiconductor layers with optimized thickness are used, then sensitivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the thickness parameters of the epitaxial semiconductor layers through systematic variation and characterization. By establishing specific thickness ranges for the alternating n-type and p-type layers, the patent achieves optimal sensitivity while keeping manufacturing precision requirements within the capabilities of standard epitaxial growth processes. The parameter optimization balances performance improvement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves sensitivity and reduces residual offsets, enabling higher accuracy in direct angle sensor and 3D Hall sensor ICs by optimizing the epitaxial semiconductor layer thickness and symmetry, while maintaining compatibility with CMOS manufacturing processes.
Implementation Method 1
A vertical Hall element is established on a first wafer, comprising a low-doped epitaxial semiconductor layer with n-type conductivity
Data Source
AI summary
A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.