Stacked Hard Mask Layers for Self-Aligned Double Exposure
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in achieving fine pattern resolution and depth of focus due to limitations in light source wavelength and exposure equipment numerical aperture, particularly in controlling overlay accuracy for double exposure techniques.
Innovation Solution
A self-aligned double exposure method using a stacked structure of hard mask layers and isotropic etching to form fine patterns, simplifying the fabrication process and improving integration and yield by employing a modified hard mask layer structure and etching methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double exposure technique is used to form fine patterns, then pattern resolution is improved, but overlay accuracy control becomes difficult
Solution Approach 1:
The patent employs self-aligned double exposure where the first hard mask layer pattern serves as the alignment reference for the second exposure. The stacked structure of hard mask layers automatically provides the alignment基准, eliminating the need for separate overlay control processes and achieving reliable overlay accuracy without additional complexity
Solution Approach 2:
The patent introduces a vertical stacked structure of multiple hard mask layers (first hard mask layer 120, second hard mask layer 130, third hard mask layer 140, fourth hard mask layer 150) to solve the overlay problem. By transitioning from a planar single-layer mask to a three-dimensional stacked mask structure, the patent achieves both fine pattern resolution and reliable overlay control through the vertical arrangement that provides self-alignment
2Manufacturing precision
If stacked hard mask layer structure is used, then critical dimension uniformity is improved, but device complexity increases
Solution Approach 1:
The patent divides the hard mask structure into multiple functional segments (first hard mask layer 120, second hard mask layer 130, third hard mask layer 140, fourth hard mask layer 150) with each layer serving a specific purpose in the pattern formation process. This segmentation allows each layer to be optimized for its specific function while collectively achieving improved critical dimension uniformity
Solution Approach 2:
The patent utilizes selective etching parameters and isotropic etching conditions to achieve uniform critical dimensions. By carefully controlling etching parameters and using isotropic etching that etches equally in all directions, the patent achieves consistent pattern dimensions across the wafer despite the increased structural complexity
Data Source
AI summary
A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask layer by using a line/space mask as an etching mask to form a second hard mask layer pattern and a first hard mask layer pattern, forming an insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer and its underlying first hard mask layer pattern by using the insulating film as an etching mask to form a fourth hard mask layer pattern overlying a third hard mask layer pattern, removing the insulating film and the fourth hard mask layer pattern, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask, to form a fine pattern.