Stacked Hard Mask Patterns for Semiconductor Trench Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device fabrication, increased integration leads to higher processing variation due to the increasing number of etching steps and depth of etched features, which traditional methods struggle to manage effectively.
Innovation Solution
A method involving the use of sequentially stacked hard mask patterns, including a metal mask pattern like titanium nitride, to form trenches and via holes with improved selectivity and reliability, using processes like wet etching and chemical mechanical polishing to minimize process variation and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photo mask etching steps are used, then fabrication process is simple, but processing variation increases with increased integration
Solution Approach 1:
The patent divides the etching process into multiple selective etching steps using sequentially stacked hard mask patterns (first hard mask pattern and second hard mask pattern). Each hard mask pattern enables selective etching of specific regions, allowing precise control over trench formation while managing the complexity of high integration devices.
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing multiple hard mask patterns at different heights and positions. The first hard mask pattern is positioned at a first height and the second hard mask pattern at a second height, enabling three-dimensional control of the etching process to achieve precise trench formation with reduced processing variation.
2Manufacturing precision
If etching depth increases with integration, then feature functionality improves, but processing variation increases
Solution Approach 1:
The patent forms the first hard mask pattern and second hard mask pattern in advance before the actual trench etching process. These pre-formed masks serve as templates that guide the subsequent selective etching, ensuring precise depth and shape control even for deep etched features required in high integration devices.
Solution Approach 2:
The hard mask patterns act as intermediary layers between the etching process and the underlying structures. The first and second hard mask patterns mediate the etching process by providing selective protection and guidance, enabling precise control of etching depth and reducing processing variation in deep feature fabrication.
3Manufacturing precision
If hard mask process is used to minimize processing variation, then etching precision improves, but process complexity increases
Solution Approach 1:
The complex masking requirement is segmented into multiple simpler hard mask patterns (first and second hard mask patterns) that can be formed and processed separately. Each mask pattern performs a specific function in the selective etching process, making the overall complex process more manageable and controllable.
Solution Approach 2:
The sequentially stacked hard mask patterns serve multiple functions: they act as etching masks, define trench geometries, control etching depth, and protect underlying structures. This multi-functionality reduces the need for additional specialized process steps, managing complexity while maintaining high etching precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process variation and improves the reliability of semiconductor devices by allowing for more precise control over trench and via hole formation, reducing the aspect ratio and preventing damage to underlying structures during etching.
Implementation Method 1
the removing of the second hard mask pattern comprises selectively removing the second hard mask pattern using wet etching
Implementation Method 2
the partially removing the filler material is performed using at least one of a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof
Data Source
AI summary
In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.