Stacked HEMT Structure for Higher Current Density in Compact Devices
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Solution Overview
Problem
Existing electronic devices with single high electron mobility transistors face limitations in current density and power handling due to high on-state resistivity, which cannot be effectively addressed by increasing the device's surface area or resizing the transistors.
Innovation Solution
The electronic device comprises two high electron mobility transistors stacked with a common source, drain, and gate electrode configuration, where the conduction layers of the transistors are connected in parallel, allowing for increased current density and reduced on-state resistivity without increasing the device's surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the surface area of the device is increased to handle higher current density, then the current carrying capacity improves, but the device size increases
Solution Approach 1:
The patent transitions from a planar single-transistor layout to a three-dimensional stacked configuration with two HEMT transistors vertically arranged. The first HEMT transistor is positioned on a first substrate and the second HEMT transistor is positioned on a second substrate, with their conduction layers connected in parallel through conductive vias. This vertical stacking approach increases current density handling capacity by utilizing the third dimension (height) rather than expanding the device footprint on the substrate plane.
2Reliability
If the transistor size is increased to reduce on-state resistivity, then the electrical conductivity improves, but the device area increases
Solution Approach 1:
The patent combines two HEMT transistors into a single integrated device structure with their conduction layers connected in parallel. The source and drain electrodes of both transistors are interconnected through conductive vias that pass through the substrate, creating parallel current paths. This merging of multiple conduction paths reduces the overall on-state resistivity without requiring each individual transistor to be larger, thereby maintaining a compact device footprint.
3Power
If two separate HEMT transistors are integrated to increase current density, then the power handling improves, but the device complexity increases
Solution Approach 1:
The patent implements a dual-substrate architecture where each substrate serves multiple functions: it supports a HEMT transistor, provides conductive vias for electrical interconnection, and acts as a mechanical support structure. The first substrate carries the first HEMT transistor and contains first conductive vias for connecting to the second substrate, while the second substrate carries the second HEMT transistor and contains second conductive vias. This multi-functional design reduces overall device complexity by consolidating support, connection, and electrical function into unified structures rather than requiring separate components for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a compact electronic device with enhanced current density and lower on-state resistivity, suitable for higher power applications without the need for resizing the transistors or increasing the device's surface area.
Implementation Method 1
each comprise, from the interface, a barrier layer and a channel layer capable of forming a conduction layer in the form of a two-dimensional electron gas
Data Source
AI summary
The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.