Stacked HEMT Assembly With Parallel Paths for Higher Current Density
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Solution Overview
Problem
Existing high electron mobility transistors (HEMTs) face challenges in increasing current density due to on-state resistivity (Ron) limitations, which are exacerbated by space constraints and complex resizing requirements.
Innovation Solution
An electronic assembly comprising stacked elementary modules with parallel-connected front and back transistors, each with shared source, drain, and gate electrodes, utilizing contact layers and connection means to enhance current density without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of a single HEMT transistor is increased to increase current density, then the current carrying capacity is improved, but the device area increases and space constraints are worsened
Solution Approach 1:
The patent divides a single large transistor into multiple smaller transistors connected in parallel. Each transistor has its own source, drain, and gate electrodes, but they share common connection regions. This segmentation allows the current to be distributed across multiple devices, achieving high current density without requiring a single large transistor that would consume excessive space.
Solution Approach 2:
The patent merges multiple transistors into a compact integrated structure where they share common source and drain connection regions. The transistors are arranged in parallel with their source electrodes connected to a common source region and drain electrodes connected to a common drain region, reducing the overall device area while maintaining high current capacity.
2Quantity of substance
If multiple transistors are stacked to increase current density, then the current carrying capacity is improved, but the vertical space and layer complexity increase
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration. Multiple transistor pairs are stacked vertically along a stacking direction, with insulator layers separating the transistors. This vertical stacking allows multiple current conduction paths to be integrated in the vertical dimension rather than requiring lateral expansion, thereby increasing current density without proportionally increasing device footprint.
3Quantity of substance
If the on-state resistance is reduced to improve current flow, then the current density is improved, but the heat generation and management complexity increase
Solution Approach 1:
By segmenting the current path into multiple parallel transistor channels, the on-state resistance is reduced as the equivalent resistance of parallel devices is lower than individual devices. The heat generation is distributed across multiple transistors and their respective source-drain paths, preventing concentration of thermal load in a single device and facilitating better heat management.
Data Source
AI summary
The disclosure concerns an electronic assembly which extends along a stacking direction from a lower surface to an upper surface coupled by an edge surface, the assembly comprises at least two elementary modules stacked along the stacking direction, which each comprise, along the stacking direction and from a back side to a front side, two high electron mobility transistors respectively called back transistor and front transistor, separated by an insulator layer, and having in common a source electrode, a drain electrode, and a gate electrode, the assembly of the front and back transistors being electrically connected in parallel, the electronic assembly comprises, arranged on the front side of each elementary module, a contact layer, electrically contacting the gate electrode of the considered elementary module from its front side, each of the contact layers comprising an electric contact point emerging onto the edge surface.