Stacked IC Power Array Layout for Low-Voltage IR Drop Reduction
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Solution Overview
Problem
High power consumption and significant IR (current times resistance) drops in integrated circuits (ICs) operating at low power supply voltages lead to inefficiencies in voltage regulation and increased I2R power losses, especially when multiple ICs are aggregated, making it challenging to achieve power savings through low voltage distribution.
Innovation Solution
The implementation of an array of devices with power supply stacking and staggered voltage distribution, where each device has a Vdd terminal and a Vss terminal, with additional V_Terz terminals, allowing for a balanced voltage generation across the array by connecting Vss terminals of subsequent devices in a column to the Vdd terminal of the previous device, and generating staggered voltages between columns using voltage dropping elements to maintain a consistent potential difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low power supply voltage (200mV-500mV) is used to reduce dynamic power dissipation, then power consumption is reduced, but IR drops and I2R power losses increase significantly due to high current requirements
Solution Approach 1:
The system segments the array of devices into multiple columns, with each column having its own dedicated voltage regulator. This segmentation distributes the high current load across multiple regulators instead of requiring one regulator to supply all current to all devices, thereby reducing I2R losses in the power distribution network while maintaining low operating voltages at each device
Solution Approach 2:
The patent introduces an intermediate power distribution architecture where voltage regulators are placed at column level rather than at a central location. This intermediate distribution point reduces the resistance of power paths by shortening current paths and reducing aggregation points, thereby reducing I2R losses while enabling low voltage operation
2Productivity
If multiple ICs are aggregated to meet high-performance compute demands, then processing capability is improved, but voltage regulation efficiency deteriorates due to large I2R drops in current aggregation paths
Solution Approach 1:
The array is segmented into multiple columns with distributed voltage regulators, allowing each column to independently regulate voltage for its devices. This eliminates the need to aggregate high currents through long resistance paths from a single regulator, thereby maintaining voltage regulation efficiency while supporting high-performance compute demands through parallel device operation
Solution Approach 2:
The patent transitions from a centralized power distribution model to a distributed column-based model, adding a spatial dimension to power regulation. By organizing devices in a two-dimensional array with column-wise power distribution, the system reduces current path lengths and resistance aggregation, improving voltage regulation efficiency while maintaining high compute capability
3Power
If series power supply stacking is used to reduce current requirements, then current demand is reduced, but additional voltages and power saving techniques become unavailable
Solution Approach 1:
Instead of using series stacking which would reduce current but eliminate voltage flexibility, the patent segments the system into multiple columns with independent voltage regulators. Each regulator can independently adjust its output voltage, maintaining adaptability and versatility while distributing the power load to reduce current requirements through parallel rather than series configuration
Solution Approach 2:
The patent implements dynamic voltage regulation in each column, allowing voltage levels to be adjusted based on the specific needs of devices in each column. This dynamic adaptability maintains versatility while the distributed architecture reduces current requirements compared to a centralized approach, without the constraints of series stacking
Data Source
AI summary
Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M−1.