Stacked IC Package Interconnects for Higher Bandwidth Density

The patent transitions from planar interconnection structures to three-dimensional stacked interconnection structures. Multiple interconnect layers are stacked vertically with through-silicon vias (TSVs) providing vertical interconnections between layers, enabling high-density interconnects by utilizing the vertical dimension rather than only horizontal routing.

The patent implements nested interconnection structures where conductive traces are embedded within dielectric layers, and multiple such layers are stacked within the package. Through-silicon vias nest through the substrate to connect different stacked devices, creating a nested configuration that maximizes interconnect density within the available volume.

The patent divides the interconnection structure into discrete modular layers, each containing conductive traces and dielectric materials. Through-silicon vias are segmented into distinct formation and filling steps. This segmentation allows each layer and component to be manufactured and tested independently, improving overall manufacturing precision despite high density requirements.

The patent employs preliminary formation of via holes through the silicon substrate before depositing conductive materials. Dielectric layers are pre-formed and patterned before subsequent interconnect layers are added. These preliminary actions establish precise geometric constraints that guide subsequent manufacturing steps, maintaining precision throughout the multi-layer fabrication process.