Stacked IC BEOL Bonding Layout for Overlay Precision
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Solution Overview
Problem
The downscaling of integrated circuit (IC) devices poses challenges in maintaining overlay precision and minimizing bending distortion and overlay errors as semiconductor substrates become thinner and pattern sizes are reduced, affecting critical dimension uniformity and reliability.
Innovation Solution
The IC device incorporates a back-side power delivery network (BSPDN) structure with a wiring structure on the substrate backside, utilizing a first and second BEOL structure separated by a second semiconductor substrate with locally bonded surfaces and air gaps, minimizing bending distortion and overlay errors through precise pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the semiconductor substrate becomes thinner to achieve higher integration, then device integration density is improved, but bending distortion and overlay errors increase
Solution Approach 1:
The patent divides the single substrate system into two separate substrates (first substrate with FEOL and second substrate with BEOL) that are bonded together. This segmentation allows each substrate to be processed independently with optimal thickness for its specific function, eliminating the bending distortion that occurs in thin single substrates while maintaining high integration density through the bonded structure.
Solution Approach 2:
The patent transitions from a planar single-substrate architecture to a three-dimensional stacked architecture with two substrates bonded face-to-face. This dimensional change enables independent optimization of each substrate's thickness and structural properties, resolving the contradiction between thin substrate requirements for integration and thick substrate requirements for mechanical stability.
2Quantity of substance
If the semiconductor substrate becomes thinner to achieve higher integration, then device integration density is improved, but bending distortion increases
Solution Approach 1:
By segmenting the device into two separately processed substrates that are subsequently bonded, each substrate can maintain optimal mechanical stability with appropriate thickness for its specific layer (FEOL or BEOL), eliminating the bending distortion inherent in thin single substrates while achieving high integration through the stacked configuration.
Solution Approach 2:
The two substrates act as mutual structural supports, with each substrate providing mechanical reinforcement to the other. This counterbalancing effect eliminates bending distortion by distributing mechanical stresses across both substrates rather than relying on a single thin substrate to maintain structural integrity.
3Quantity of substance
If pattern sizes are reduced to achieve higher integration, then device integration density is improved, but overlay errors increase
Solution Approach 1:
The patent segments the fabrication process into separate processing stages for two different substrates, allowing each substrate to be processed with optimal pattern sizes and overlay tolerances for its specific requirements. This eliminates the compounding overlay errors that occur when attempting to form all patterns on a single thin substrate with reduced feature sizes.
Data Source
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Figure 3A
AI summary
An integrated circuit device (100) includes a first semiconductor substrate (102) having a frontside surface (102F) and a backside surface (102B) opposite to each other, an FEOL structure (FS) on the frontside surface (102F) of the first semiconductor substrate (102), a first BEOL structure (BS1) on the FEOL structure (FS), a second BEOL structure (BS2) on the backside surface (102B) of the first semiconductor substrate (102), and a second semiconductor substrate (104) apart from the first semiconductor substrate (102) in a vertical direction with the FEOL structure (FS) and the first BEOL structure (BS1). The second semiconductor substrate (104) is locally bonded to the first BEOL structure (BS1). The second semiconductor substrate (104) includes a main surface (104S) facing the first BEOL structure (BS1), and the main surface (104S) of the second semiconductor substrate (104) defines a local trench region in which trenches are defined in a regular pattern and local bonding areas bonded to the first BEOL structure (BS1).