Stacked IC Package With Capacitive Die Isolation
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Solution Overview
Problem
Existing IC packages face limitations in achieving galvanic isolation between dies with different voltage levels, restricting the use of diverse materials and processing techniques for each die.
Innovation Solution
The IC package design incorporates a first and second die with a dielectric layer sandwiched between protective overcoats, forming a capacitor that couples the dies while maintaining galvanic isolation, allowing for different materials and processing techniques based on each die's operating parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dies with different voltage levels are connected directly, then electrical connection and signal transmission are achieved, but galvanic isolation is lost and ground loops occur
Solution Approach 1:
A capacitor is introduced as an intermediary element between the first die and second die to provide galvanic isolation. The capacitor couples the two dies electrically while blocking direct current flow, thereby preventing ground loops and allowing each die to operate at different voltage levels without direct galvanic connection.
Solution Approach 2:
The connection between dies transitions from a planar side-by-side configuration to a vertical stacked configuration. The first die is positioned above the second die with the capacitor intervening between them, utilizing the vertical dimension to achieve both compact packaging and electrical isolation.
2Reliability
If a capacitor is introduced to achieve galvanic isolation, then electrical isolation and ground loop prevention are achieved, but device complexity and manufacturing steps increase
Solution Approach 1:
The capacitor fabrication process is merged with the standard die stacking process. The capacitor is formed as an integrated structure during the same manufacturing sequence used to create the die connections, rather than being added as a separate discrete component, thereby simplifying the overall manufacturing process.
3Productivity
If dies are stacked vertically with capacitor coupling, then compact packaging and galvanic isolation are achieved, but alignment precision between metal pads is required
Solution Approach 1:
The metal pads on both dies are designed with matching geometries and are positioned to achieve optimal capacitive coupling. The pads are formed to extend toward each other across the capacitor interface, ensuring consistent electrical characteristics and facilitating precise alignment during the stacking process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves electrical isolation, enabling communication between dies with different ground potentials and allowing for independent selection of materials and processes, enhancing flexibility and efficiency in high-voltage applications.
Implementation Method 1
The first metal pad and the second metal pad form a capacitor that couples the first die with the second die
Implementation Method 2
a dielectric layer having a first surface contacting the second surface of the first die
Data Source
AI summary
An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.