Stacked IC Integrated Capacitor Layout for PDN Noise Suppression
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Solution Overview
Problem
Stacked integrated circuit devices face challenges in power distribution noise suppression due to their small footprint, which complicates capacitive decoupling and increases power distribution inefficiencies, especially in 3D IC architectures where space for noise suppression capacitors is limited and inductance parasitics degrade performance.
Innovation Solution
Incorporating an integrated capacitor device (ICD) within the stacked IC architecture, positioned adjacent to the lower die and electrically coupled to the power distribution network (PDN), utilizing deep trench capacitors or multilayer ceramic capacitors to provide effective capacitive decoupling and reduce inductance, thereby improving PDN performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If stacked IC architecture is used to reduce footprint, then device integration density is improved, but power distribution noise suppression capability deteriorates
Solution Approach 1:
The patent transitions from 2D planar capacitor placement to 3D vertical stacking, positioning capacitors in the z-dimension between dies. This dimensional change allows capacitors to be placed in overhang regions without increasing the device footprint, while maintaining effective decoupling performance through reduced inductance paths.
Solution Approach 2:
The patent embeds capacitors within the stacked IC structure by placing them in overhang regions between dies. The capacitors are nested within the vertical stack configuration, utilizing the space between the lower die and substrate, effectively integrating noise suppression functionality into the compact 3D architecture.
2Area of moving object
If footprint is reduced for mobile devices, then space for noise suppression capacitors is limited, but power distribution efficiency deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension to place capacitors between dies in the stack, eliminating the need for increased footprint. This 3D placement maintains short current paths and low inductance, preserving power distribution efficiency without sacrificing device compactness.
Solution Approach 2:
The patent places capacitors specifically in overhang regions where the lower die extends beyond the substrate or lower layers. This localized placement strategy provides effective decoupling exactly where needed in the power distribution network, optimizing energy efficiency in the critical regions without requiring overall device expansion.
3Object-affected harmful factors
If capacitive decoupling is implemented in stacked IC, then power distribution noise is suppressed, but inductance parasitics increase
Solution Approach 1:
The patent converts the potential harm of inductance parasitics into a benefit by strategically placing capacitors in overhang regions that minimize current loop areas. The close proximity of capacitors to power delivery paths in the vertical stack reduces loop inductance, transforming what could be a harmful parasitic effect into an optimized power distribution solution.
Solution Approach 2:
The patent performs preliminary placement of capacitors in overhang regions during the stacking process, establishing optimal decoupling positions before final assembly. This preliminary positioning ensures minimal inductance paths are created from the outset, preventing rather than correcting inductance issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of ICDs in overhang regions between dies in the stacked IC structure enhances power distribution network performance by reducing inductance and increasing the effectiveness of noise suppression, leading to improved power distribution efficiency and reduced manufacturing complexity.
Implementation Method 1
an integrated capacitor device (ICD) coupled to the first side of the first die. The ICD is electrically connected, via the first set of contacts, to the PDN
Data Source
AI summary
A stacked integrated circuit (IC) device includes a first die including active circuitry and a power distribution network (PDN). The first die has a first set of contacts on a first side of the first die. The stacked IC device also includes a second die coupled, on a first side of the second die, to the first side of the first die. The second die also includes, on a second side of the second die, a second set of contacts to electrically connect circuitry of the second die to a substrate. The stacked IC device also includes an integrated capacitor device (ICD) coupled to the first side of the first die. The ICD is electrically connected, via the first set of contacts, to the PDN and includes one or more through-ICD conductors to electrically connect the PDN to the substrate.