Stacked IC Mirror Structure for Chip Distinction and Power I/O Control
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Solution Overview
Problem
Current stacked integrated circuits lack an effective method to distinguish between chips within stacked configurations, which is essential for testing and operation.
Innovation Solution
A stacked integrated circuit design where upper and lower chips are rotated around a rotation axis and stacked in a mirror symmetric structure, with each chip generating internal distinguishment signals and input/output control signals to manage power and chip selection, enabling differentiation and control of power signals between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked together to improve integration degree, then the degree of integration is improved, but the ability to distinguish and test individual chips deteriorates
Solution Approach 1:
The patent divides the stacked chip system into independently controllable segments by generating distinct internal distinguishment signals for each chip. Each chip receives a unique signal (first internal distinguishment signal for upper chip, second internal distinguishment signal for lower chip) that enables individual identification and testing while maintaining the stacked configuration.
Solution Approach 2:
The patent introduces an intermediary distinguishment signal generation mechanism that acts as a mediator between the stacked chips and the testing system. This intermediary system generates and distributes unique internal distinguishment signals to each chip, enabling the testing system to differentiate between chips without physically separating them.
2Ease of manufacture
If chips are stacked in a conventional configuration, then manufacturing is simplified, but the control and input/output management of power signals between chips becomes complex
Solution Approach 1:
The patent applies local quality by generating specific input/output control signals tailored to each chip's position and characteristics. The upper chip receives a first input/output control signal while the lower chip receives a second input/output control signal, allowing customized control of power signals for each chip based on its specific requirements in the stacked configuration.
Solution Approach 2:
The patent introduces dynamic control capabilities by enabling independent generation and modification of internal distinguishment signals and input/output control signals for each chip. This dynamic signal generation allows flexible control of power signal input and output for each chip, adapting to different operational requirements without changing the physical stacked structure.
Data Source
AI summary
A stacked integrated circuit includes an upper chip that is rotated around a rotation axis and stacked on a lower chip in the form of a mirror symmetric structure. The lower chip and the upper chip are stacked in the form of a front and front connection structure. The upper chip is configured to generate a first internal distinguishment signal based on a distinguishment signal. The upper chip is configured to generate a first input/output control signal for the input/output of a power signal based on the first internal distinguishment signal and a chip selection signal. The lower chip is configured to generate a second internal distinguishment signal based on a reset signal. The lower chip is configured to generate a second input/output control signal for the input/output of the power signal based on the second internal distinguishment signal and the chip selection signal.