Stacked IC Interconnect Structure with Dielectric-Isolated Deep Plugs
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Solution Overview
Problem
Existing stacked IC devices and fabrication methods do not fully satisfy the need for improved density and efficiency in semiconductor devices, as they lack effective techniques for achieving high-density integration and efficient interconnects between wafers.
Innovation Solution
A method for fabricating a stacked IC device involves bonding semiconductor wafers using direct bonding techniques, forming a dielectric block and deep-interconnection-trenches, and filling these trenches with conductive materials to create deep-interconnect-plugs, which provide improved process window and flexibility in lithography and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bonding techniques are used for stacking semiconductor wafers, then device integration is achieved, but manufacturing precision and process flexibility are insufficient
Solution Approach 1:
The patent applies preliminary action by forming the dielectric block and deep-interconnection-trenches in the first semiconductor wafer before bonding to the second wafer. This pre-preparation of interconnect structures enables precise alignment and reduces manufacturing complexity during the bonding process, as the trenches are already positioned and sized correctly for receiving conductive materials that will establish electrical connections.
Solution Approach 2:
The patent segments the interconnect structure into distinct components: dielectric blocks, deep-interconnection-trenches, and conductive material regions. This segmentation allows each component to be optimized independently - the dielectric block provides isolation, the trenches provide precise conductive pathways, and the conductive materials establish electrical connections - thereby improving manufacturing precision while maintaining process flexibility.
2Quantity of substance
If direct bonding techniques are used to bond semiconductor wafers, then device integration is achieved, but interconnect density and electrical isolation are insufficient
Solution Approach 1:
The patent implements the nested doll principle by placing conductive materials within deep-interconnection-trenches that are themselves contained within or adjacent to dielectric blocks. This nested structure - conductive material inside trenches, trenches surrounded by dielectric - enables high interconnect density while maintaining reliable electrical isolation, as each conductive pathway is independently enclosed and isolated from adjacent interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the density and efficiency of stacked IC devices by enabling precise and flexible interconnects between wafers, improving the integration of semiconductor elements and reducing physical size while maintaining electrical isolation and conductivity.
Implementation Method 1
bonding semiconductor wafers using direct bonding techniques
Data Source
AI summary
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.