Stacked IC Die Interconnects for Mixed-Size 3D Packaging
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Solution Overview
Problem
Efficiently implementing a compact integrated circuit package with stacked integrated circuit dies of different sizes is challenging due to the requirement of matching die sizes in wafer-to-wafer manufacturing processes, which limits the types of dies used and system performance.
Innovation Solution
The solution involves forming inter-die connections using hybrid bonds, micro-bumps, or other suitable structures between integrated circuit dies of varying sizes, allowing for the stacking of dies with different technology nodes and sizes, and using redistribution layers to facilitate electrical connections and fan-in/fan-out structures for efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-to-wafer manufacturing processes are used to implement stacked integrated circuit dies, then manufacturing efficiency is improved, but die size matching requirements limit the types of dies that can be used and restrict system performance optimization
Solution Approach 1:
The patent segments the manufacturing process into two independent stages: first, wafers are processed and diced into individual dies separately; second, the diced dies are stacked and bonded together. This segmentation allows each die to be manufactured at its optimal size without requiring size matching during stacking, thereby resolving the contradiction between manufacturing efficiency and die size compatibility.
Solution Approach 2:
The patent performs preliminary actions by completing all wafer processing and die formation before the stacking operation. Dies are fully fabricated, tested, and prepared in advance on their respective wafers, then diced and stacked. This preliminary preparation eliminates the need for size matching during the stacking process itself, enabling both high productivity and die size versatility.
2Reliability
If dies of different sizes are stacked to optimize system performance, then system performance is improved, but implementing compact packaging becomes difficult due to size matching requirements
Solution Approach 1:
By separating die fabrication from die stacking, the patent enables each die to be optimized for its specific function and size requirements. Smaller dies can be used for high-performance logic functions while larger dies can accommodate memory arrays or sensor elements, allowing system performance optimization without compromising packaging simplicity.
Solution Approach 2:
The patent applies local quality by allowing different dies in the stack to have different sizes, materials, and fabrication characteristics appropriate to their specific functional requirements. Each die can be customized with optimal dimensions for its particular role in the system, whether that requires a compact logic die or a larger memory die, thereby improving overall system performance without increasing packaging complexity.
3Ease of manufacture
If die sizes are matched in wafer-to-wafer processes, then manufacturing simplicity is maintained, but the ability to use different technology nodes and optimize each die's performance is limited
Solution Approach 1:
The patent divides the manufacturing workflow into independent die fabrication stages followed by a separate stacking stage. This allows each die to be manufactured using the most appropriate technology node and process optimizations for its specific function, while the stacking process remains simple and standardized. The segmentation eliminates the constraint that previously forced all dies to use matching sizes and technology nodes.
Solution Approach 2:
The patent changes the critical parameter from die size matching to die interface compatibility. By focusing on ensuring compatible electrical and mechanical interfaces rather than matching physical dimensions, the patent enables flexibility in die size, technology node, and material selection while maintaining manufacturing simplicity through standardized stacking and bonding procedures.
Data Source
AI summary
An integrated circuit package (34, 34′, 34″) may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).