Stacked IC Die Signal Routing Interconnects for Thermal Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic assemblies with stacked integrated circuit (IC) die face challenges in efficient signal routing and heat dissipation due to high thermal resistance and undesirable electrical characteristics, particularly when using direct chip attach with wirebonds and packaged die that interfere with top-side heatsinking.
Innovation Solution
The electronic assembly employs a signal routing interconnect system with conductive traces on a substrate and interconnects between IC dies, providing a low-resistance thermal path and facilitating top-side heatsinking, using electrically conductive and non-conductive substrates with conductive elements to couple contacts to traces, and incorporating a case with an integrated heatsink for improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct chip attach with wirebonds is used, then electrical connection between substrate and die is achieved, but top-side heatsinking is interfered with and thermal resistance increases
Solution Approach 1:
The patent introduces an intermediary substrate layer positioned between the IC die and the heatsink. This substrate provides both electrical insulation and thermal conduction pathways, allowing heat to be efficiently removed from the bottom of the die while the wirebonds connect electrical contacts on the top surface to the substrate. This resolves the contradiction by mediating between the electrical connection requirement and the heat removal requirement.
2Ease of operation
If packaged die with electrically insulative layers are used, then signal routing between die is achieved, but thermal resistance becomes relatively high
Solution Approach 1:
The patent employs a composite substrate structure combining electrically insulative materials with thermally conductive materials. The substrate includes insulative layers for signal routing capability while incorporating thermally conductive pathways (such as metal traces or embedded heat spreaders) that provide low thermal resistance. This composite approach allows simultaneous achievement of electrical insulation for signal routing and thermal conduction for heat removal.
3Ease of operation
If conventional signal routing techniques are used, then signal connection between stacked die is achieved, but device complexity and footprint increase
Solution Approach 1:
The patent transitions from planar signal routing to three-dimensional routing through the substrate. Electrical contacts on the die connect vertically to the substrate, and signal traces are routed within the substrate layers before emerging at different locations. This dimensional transition allows compact signal routing between stacked die without requiring large lateral footprint, as connections are established through the thickness of the substrate rather than across its surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances electrical and thermal performance by reducing impedance, inductance, and electromagnetic interference, while minimizing die solder joint stress and process time, and achieving efficient heat removal with a reduced footprint and improved heat dissipation.
Implementation Method 1
the case includes an integrated heatsink. In this embodiment, the base substrate is in thermal contact with a portion of the case and the second interconnect is in thermal contact with the heatsink
Data Source
AI summary
An electronic assembly (100) with a plurality of stacked integrated circuit (IC) die includes a base substrate (102), a first IC die (114B), a second IC die (114A), a signal routing first interconnect (140) and a signal routing second interconnect (120). The first interconnect (140) is partially positioned between the first and second IC dies (114B,114A). The second interconnect (120) is partially positioned adjacent the first side of the second IC die (114A). The first interconnect (140) couples a first contact of the first IC die (114B) to a first trace of the base substrate (102) and a second contact of the second IC die (114A) to a second trace of the base substrate (102). The first and second interconnects (140,120), in combination, couple the first contact of the second IC die (114A) to the first trace.