Vertically Stacked IC Dies With Nanotwinned Copper Edge Bonding
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Solution Overview
Problem
Current packaging architectures for integrated circuits (ICs) in Multi-Chip Modules (MCMs) are limited in their ability to scale to next-generation servers with signal speeds greater than 10 GHz and data speeds of 3-10 Terabytes per second due to bandwidth reduction, signal delay, and signal distortion, primarily because IC dies are oriented parallel to each other and interconnected by conventional interconnects.
Innovation Solution
The use of nanotwinned copper (NTC) for direct bonding between IC dies in a vertically stacked configuration, allowing for electrical coupling at a lateral edge, which facilitates lower-temperature copper-to-copper joint formation and reduces grain coarsening, thereby enhancing signal conductivity and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IC dies are oriented parallel to each other and interconnected by conventional interconnects, then the packaging architecture is simple to manufacture, but bandwidth reduction and signal delay occur at signal speeds greater than 10 GHz
Solution Approach 1:
The patent transitions from conventional parallel (2D) die arrangement to a vertical (3D) stacked configuration. Multiple IC dies are arranged in vertical layers and interconnected through lateral edges using direct copper-to-copper bonding, enabling three-dimensional integration. This dimensional change reduces signal path length and eliminates bandwidth reduction issues while maintaining manufacturing feasibility through direct bonding technology.
Solution Approach 2:
The patent replaces conventional mechanical interconnect structures (wire bonds, solder bumps, substrate traces) with direct copper-to-copper bonding at lateral edges. This substitution eliminates the need for intermediate substrates and complex interconnect mechanisms, directly joining copper conductors across die interfaces to achieve high-speed signal transmission without bandwidth reduction.
2Reliability
If nanotwinned copper is used for direct bonding between IC dies, then signal conductivity and heat dissipation are enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes nanotwinned copper (NTC) with specific crystallographic parameters (twin boundary spacing of 10-100 nm, <100> orientation) to achieve superior electrical and thermal properties. The NTC layer is formed through controlled electroplating processes that generate the nanotwinned structure, providing enhanced signal conductivity and thermal dissipation while maintaining compatibility with standard semiconductor manufacturing workflows.
Solution Approach 2:
The patent employs nanotwinned copper as a composite material structure within the interconnect system. The NTC layer is integrated between the copper conductors of adjacent dies, creating a composite interconnect system that combines the advantages of nanoscale twin boundaries (enhanced conductivity, grain boundary strengthening) with macro-scale direct bonding architecture. This composite approach improves signal transmission and heat dissipation without requiring complete redesign of the manufacturing process.
3Area of stationary object
If IC dies are vertically stacked with direct bonding, then more high-power compute IC dies can be stacked within constrained footprint, but grain coarsening occurs at elevated temperatures
Solution Approach 1:
The patent controls copper grain structure parameters through nanotwinned copper formation with specific twin boundary spacing (10-100 nm) and crystallographic orientation (<100>). These parameter changes create a stable nanoscale structure that resists grain coarsening during subsequent thermal processing. The high density of twin boundaries acts as pinning sites that prevent grain growth, maintaining fine-grained structure even after reflow and annealing processes required for direct bonding.
Solution Approach 2:
The patent applies preliminary anti-action by forming the nanotwinned copper structure before the direct bonding process. The NTC layer is created with controlled twin boundaries that preemptively counteract the grain coarsening tendency during subsequent thermal cycles. This preliminary structuring prevents the harmful grain growth that would otherwise occur during bonding, ensuring stable electrical and mechanical properties throughout the device lifecycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher current conduction and improved thermal stability, overcoming the limitations of conventional interconnects by allowing more high-power compute IC dies to be stacked within a constrained footprint, thus meeting the bandwidth and speed requirements of next-generation servers.
Implementation Method 1
The use of nanotwinned copper (NTC) for direct bonding between IC dies in a vertically stacked configuration, allowing for electrical coupling at a lateral edge, which facilitates lower-temperature copper-to-copper joint formation
Implementation Method 2
facilitates lower-temperature copper-to-copper joint formation and reduces grain coarsening
Implementation Method 3
enables higher current conduction and improved thermal stability, overcoming the limitations of conventional interconnects by allowing more high-power compute IC dies to be stacked
Implementation Method 4
enhancing signal conductivity and heat dissipation
Data Source
AI summary
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, an opposing second surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface with conductive contacts, wherein the conductive traces exposed at the third surface of the first IC die are electrically coupled to the conductive contacts at the fourth surface of the second IC die by metal-metal bonds including nanotwinned copper and dielectric-dielectric bonds. In some embodiments, the first IC die may be one of a plurality of first IC dies. In such embodiments, some of the plurality of first IC dies may include memory circuitry and some of the plurality of first IC dies may include compute circuitry.