Vertically Stacked IC Dies With Multi-Side Routing for Heat and Bandwidth
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Solution Overview
Problem
Current Multi-Chip Module (MCM) packaging architectures are limited in scaling to higher bandwidth and data speeds due to signal delay, loss, and distortion, primarily because IC dies are stacked parallel to each other, which restricts the placement of high-power compute IC dies and limits the package's ability to handle heat dissipation effectively.
Innovation Solution
The proposed solution involves coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds, allowing for a metallization stack with conductive traces parallel to one surface and orthogonal to the other, enabling vertical stacking and improved heat dissipation while maintaining electrical connectivity through conductive vias and bond-pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dies are stacked parallel to each other in traditional MCM packaging, then the package structure is simple and easy to manufacture, but the bandwidth and data speed are limited due to signal delay, loss, and distortion
Solution Approach 1:
The patent transitions from traditional parallel stacking of IC dies to a vertical stacking architecture where dies are arranged in multiple tiers along the vertical dimension. This dimensional change reduces signal transmission distance and enables higher bandwidth operations by utilizing the vertical space within the package rather than expanding horizontally.
Solution Approach 2:
The package is divided into multiple tiers with each tier containing IC dies and interconnect structures. The segmentation allows independent optimization of each tier's signal paths and enables parallel data transmission channels, thereby increasing overall bandwidth while managing signal integrity through controlled segment lengths.
2Power
If high-power compute IC dies are placed in the package, then computing power increases, but heat dissipation becomes more difficult with traditional parallel stacking
Solution Approach 1:
The vertical stacking architecture provides enhanced thermal management by creating multiple tiers that facilitate heat dissipation in the vertical direction. Heat can be conducted through the stacked structure to dedicated thermal interface areas, and the vertical arrangement allows for more effective use of thermal vias and heat sinks positioned at different elevations within the package.
Solution Approach 2:
Different regions of the vertical stack are optimized for specific functions: compute-intensive IC dies are positioned in tiers with enhanced cooling provisions, while memory or I/O dies are placed in tiers with different thermal characteristics. This local optimization allows high-power compute dies to be accommodated without compromising overall thermal management.
3Productivity
If vertical stacking with orthogonal surfaces is implemented, then heat management and density improve, but the manufacturing complexity increases due to oxide-oxide and metal-metal bonding requirements
Solution Approach 1:
The bonding surfaces are prepared in advance with precise planarization and patterning of bonding pads before stacking. Oxide layers and metal interconnect structures are pre-formed on each die surface, allowing for aligned bonding when tiers are stacked. This preliminary preparation reduces the complexity of the actual bonding process by ensuring all surfaces are ready for immediate joining.
Solution Approach 2:
Oxide layers are used as intermediary bonding surfaces between metal interconnect structures of adjacent tiers. The oxide-oxide bonding provides a stable interface that facilitates metal-to-metal electrical connectivity while managing thermal expansion differences. This intermediary approach simplifies the overall bonding process by decoupling the mechanical bonding function from the electrical connectivity function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ability to scale MCMs to higher bandwidth and data speeds by allowing for more efficient heat management and increased density of high-power compute IC dies, addressing the limitations of traditional parallel stacking methods.
Implementation Method 1
coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds
Implementation Method 2
coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds
Implementation Method 3
maintaining electrical connectivity through conductive vias and bond-pads
Data Source
AI summary
Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.