Package architectures having vertically stacked dies with solder interconnects
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Solution Overview
Problem
Current packaging architectures for Multi-Chip Modules (MCMs) are limited in their ability to scale to higher bandwidth and data speeds due to bandwidth reduction, signal delay, signal loss, and signal distortion, primarily because of the parallel configuration of IC dies.
Innovation Solution
The proposed solution involves vertically stacking IC dies and electrically coupling them laterally, using interconnects such as solder, to form a microelectronic assembly. This configuration allows for improved thermal management and increased density of high-power compute IC dies within a limited footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IC dies are arranged in parallel configuration, then electrical connectivity between dies is achieved, but bandwidth reduction, signal delay, signal loss, and signal distortion occur limiting scalability
Solution Approach 1:
The patent transitions from a two-dimensional parallel arrangement of IC dies to a three-dimensional vertical stacking configuration. Multiple IC dies are stacked vertically and interconnected through lateral edges using solder interconnects, thereby adding the vertical dimension to the traditional planar layout. This dimensional change enables increased density and improved thermal management while maintaining electrical connectivity.
2Power
If the number of high-power compute IC dies is increased within limited footprint, then processing power is improved, but thermal management becomes more challenging
Solution Approach 1:
By stacking IC dies vertically in the third dimension rather than expanding horizontally, the patent increases processing power within a limited footprint. The vertical configuration improves thermal management by exposing multiple surfaces for heat dissipation and enabling better thermal coupling to heat sinks, thereby addressing thermal challenges associated with high-density packing.
Solution Approach 2:
The patent applies different thermal management strategies to different regions of the stacked structure. Thermal interface materials and heat dissipation structures are strategically positioned at specific locations such as the bottom surface and lateral edges of the stack, optimizing heat removal from high-power compute IC dies while maintaining electrical and mechanical integrity.
3Productivity
If vertically stacked IC dies are laterally coupled using solder interconnects, then thermal dissipation is enhanced and density is increased, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary alignment and positioning structures on the IC dies before the soldering process. Alignment marks, positioning protrusions, or pre-formed solder bumps are prepared in advance to facilitate precise lateral coupling during assembly, thereby reducing manufacturing complexity and improving yield despite the three-dimensional configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical stacking and lateral coupling of IC dies enhance thermal dissipation, increase the number of high-power compute IC dies that can be packed, and improve electrical connectivity, thereby addressing the limitations of current MCM packaging architectures.
Implementation Method 1
vertically stacking IC dies and electrically coupling them laterally, using interconnects such as solder
Implementation Method 2
This configuration allows for improved thermal management and increased density of high-power compute IC dies
Data Source
AI summary
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.