Vertically Stacked IC Dies With Edge Coupling for Faster Signal Delivery
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Solution Overview
Problem
Current IC packaging architectures are limited in their ability to scale to next-generation servers due to bandwidth reduction, signal delay, and signal distortion, particularly when multiple processors are coupled together, and integrating voltage converters into vertically stacked IC dies is challenging due to limited footprint and extended power delivery distances.
Innovation Solution
The implementation of vertically stacked IC dies with lateral edge coupling and integrated voltage converters, where IC dies are serially connected to facilitate power delivery and reduce complexity, using oxide-oxide and metal-metal bonds for interconnects, and conductive traces and vias for efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are coupled together in current IC packaging architectures, then compute systems can be built, but bandwidth reduction, signal delay, and signal distortion occur
Solution Approach 1:
The patent transitions from traditional 2D planar packaging to 3D vertically stacked packaging architecture. Multiple IC dies are stacked vertically with interconnects extending laterally from side surfaces, enabling processors to be coupled in the vertical dimension rather than only in-plane. This dimensional change reduces signal path lengths and improves bandwidth while maintaining signal quality.
2Use of energy by moving object
If voltage converters are integrated into vertically stacked IC dies, then power delivery is improved, but footprint space is limited and power delivery distance is extended
Solution Approach 1:
The patent places voltage converters on vertically stacked IC dies rather than in the same planar footprint, utilizing the vertical dimension for component placement. This allows voltage converters to be integrated into the 3D stack without consuming additional footprint area, while their strategic positioning optimizes power delivery distance and efficiency.
Solution Approach 2:
The patent uses intermediate connection structures including conductive traces, vias, and interconnects that extend laterally from the vertical stack to deliver power and signals. These intermediary structures enable efficient power delivery from voltage converters to processors without requiring extended trace lengths across the footprint.
3Speed
If vertically stacked IC dies are implemented, then power delivery and signal speed are enhanced, but package complexity increases
Solution Approach 1:
The patent combines multiple IC dies, voltage converters, and interconnect structures into a single integrated 3D stacked package. This merging of components into one cohesive package structure, while increasing integration, manages complexity through systematic arrangement and standardized interconnect interfaces between stacked dies.
Data Source
AI summary
Embodiments of an integrated circuit (IC) die may include a substrate having a first surface with an array of first conductive pads, an opposite second surface, a third surface orthogonal to first and second surfaces, and through substrate vias (TSVs) electrically coupled to the array of first conductive pads; and a metallization stack having a fourth surface, an opposite fifth surface, and a sixth surface orthogonal to the fourth and fifth surfaces, and including a conductive trace parallel to the fourth and fifth surfaces and exposed at the sixth surface, and conductive vias between the fourth and fifth surfaces and exposed at the fifth surface, wherein the second surface of the substrate is coupled to the fourth surface of the metallization stack and an interface between the substrate and the metallization stack includes an array of second conductive pads electrically coupled to the conductive trace and conductive vias.