Monolithic Stacked IC Layer-by-Layer Fault Testing
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Solution Overview
Problem
Conventional fault testing methods for monolithic stacked integrated circuits are inadequate as they require complete logic across multiple layers, leading to yield loss and inefficiencies, as they cannot effectively detect defects until all layers are built, which is not feasible in monolithic stacked IC manufacturing.
Innovation Solution
Implementing a layer-by-layer fault testing approach, known as known-good-layer (KGL) testing, where Design for Test (DFT) circuits and automatic test pattern generation are used to detect faults as each layer is fabricated, utilizing scan test architecture and test pattern generation to identify defects early in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fault testing methods are used for monolithic stacked ICs, then complete logic can be tested, but all layers must be built before testing which causes significant yield loss and delays defect detection
Solution Approach 1:
The patent segments the fault testing process by layer, allowing each layer to be tested independently as it is fabricated. This enables defect detection during the manufacturing process itself rather than requiring completion of all layers first, thereby improving productivity while maintaining reliable fault detection capability.
Solution Approach 2:
The patent implements preliminary fault detection by testing each layer immediately after fabrication before proceeding to subsequent layers. This preliminary action identifies defects early in the manufacturing process, preventing yield loss and improving overall manufacturing efficiency without compromising detection reliability.
2Loss of time
If layer-by-layer fault testing is implemented, then defect detection timing is improved, but test architecture complexity increases
Solution Approach 1:
The test architecture is segmented into layer-specific test sequences, where each layer has dedicated test patterns and verification steps. This segmentation enables early defect detection while managing complexity through modular, layer-by-layer testing rather than requiring a completely complex monolithic test system.
Solution Approach 2:
Test patterns and verification circuits are prepared in advance for each layer before fabrication begins. This preliminary preparation simplifies the actual testing process during manufacturing, reducing on-the-fly complexity while enabling timely defect detection as each layer is completed.
3Adaptability or versatility
If complete logic spans multiple layers, then functional complexity is achieved, but fault testing becomes infeasible until all layers are built
Solution Approach 1:
The patent segments the multi-layer functional complexity into testable units at each layer level. By dividing the overall fault testing into layer-specific segments, the system can test individual layers independently while still supporting the complete complex functionality across all layers, making fault testing feasible without sacrificing functional complexity.
Solution Approach 2:
The patent prepares layer-specific test patterns and verification mechanisms in advance, enabling fault testing to be performed as each layer is fabricated. This preliminary action makes fault testing feasible during the manufacturing process itself, allowing early defect detection while maintaining the ability to support complex multi-layer functionality.
Data Source
AI summary
A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its upper layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.