Stacked IC Gate Discharge Path for Charge Breakdown Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional integrated circuit devices face challenges in secure isolation between stacked transistors, leading to potential issues with charge accumulation and gate dielectric breakdown.
Innovation Solution
The integration of a diode structure as part of a discharging path between the gate electrode of the upper transistor structure and the substrate, which extends through an isolation layer, provides a pathway for charges to dissipate and reduces the risk of accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked transistor structures are used to increase device density, then productivity is improved, but charge accumulation occurs leading to gate dielectric breakdown and reduced reliability
Solution Approach 1:
The patent segments the gate structure into multiple stacked gates (first gate electrode, second gate electrode, third gate electrode) separated by isolation layers. This segmentation allows independent control and charge dissipation paths for each gate, preventing charge accumulation that would occur in a single monolithic gate structure, thereby maintaining reliability while achieving high density.
Solution Approach 2:
The patent introduces discharging paths as intermediary structures between the stacked gates and the substrate. These discharging paths, formed through the isolation layers, act as mediators that safely conduct accumulated charges away from the gate dielectrics, preventing breakdown while allowing the stacked configuration to maintain high device density.
2Reliability
If isolation layers are added between stacked transistors to prevent charge accumulation, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the isolation layers: they serve as both electrical isolators between stacked gates and as pathways for charge dissipation. By combining these functions, the patent reduces the need for additional separate structures, thereby improving reliability without proportionally increasing device complexity.
Solution Approach 2:
The isolation layers are designed with multi-functionality, serving simultaneously as electrical insulators, charge dissipation pathways, and structural support elements. This universality allows the stacked transistor structure to achieve reliable charge isolation without requiring additional dedicated components, thus limiting the increase in device complexity.
3Reliability
If discharging paths extend through isolation layers to substrate, then charge accumulation is prevented improving reliability, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the discharging paths through the isolation layers during the same manufacturing step in which the gate electrodes are formed. This preliminary action ensures proper alignment between the discharging paths and the gates without requiring subsequent alignment steps, thereby improving reliability through effective charge dissipation while limiting the increase in manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively improves the performance and reliability of the integrated circuit device by preventing charge accumulation and reducing the likelihood of gate dielectric breakdown, thereby enhancing the overall stability and efficiency of the device.
Implementation Method 1
a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the substrate.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Integrated circuit devices and methods of forming the same are disclosed. An integrated circuit device includes a substrate (112); a first transistor structure (100) on the substrate (112); a second transistor structure (200) stacked in a vertical direction (D3) on the first transistor structure (100); an isolation layer (300) between the first transistor structure (100) and the second transistor structure (200) in the vertical direction (D3); and a discharging path (DP) between a gate electrode (232) of the second transistor structure (200) and the substrate (112). The discharging path (DP) extends through the isolation layer (300) and comprises a diode structure (DS).