Stacked IC Layer Identification Circuits for 3D Semiconductor Packages
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Solution Overview
Problem
In 3D semiconductor packaging, it is challenging to distinguish between stacked chips/wafers with the same function, leading to incorrect access and failure analysis, as their electrical characteristics are indistinguishable.
Innovation Solution
A semiconductor package with identification circuits in each IC substrate, using a conductive structure to generate unique identifiers based on physical spatial relationships, allowing for precise identification and addressing of individual layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wafer-on-wafer stacking is used to increase integration density and storage capacity, then storage density and read/write speeds are improved, but the ability to distinguish between stacked chips with the same function deteriorates
Solution Approach 1:
The patent divides the identification function into separate identification circuits that are independently integrated into each wafer in the stack. Each identification circuit contains unique identification information for its specific wafer, allowing individual wafers to be distinguished despite having identical functional circuits. This segmentation of identification functionality resolves the contradiction by maintaining both high integration density and unique identifiability.
Solution Approach 2:
The patent introduces identification circuits as intermediary elements between the stacked wafers and the control system. These identification circuits act as mediators that provide unique identification information for each wafer without interfering with the functional operations of the stacked memory devices. This intermediary approach allows the system to maintain both high storage density and the ability to individually address and identify each wafer.
2Productivity
If multiple wafers with the same function are stacked, then system performance and data throughput are improved, but correct access and failure analysis become difficult
Solution Approach 1:
The patent segments the identification capability into individual identification circuits within each wafer. Each identification circuit maintains unique identification information that allows the control system to determine the specific position and status of each wafer in the stack. This enables precise failure analysis by identifying which specific wafer is malfunctioning, while simultaneously maintaining high data throughput through parallel operations on multiple wafers.
Solution Approach 2:
The patent implements feedback mechanisms where identification circuits continuously provide identification information about each wafer's status and position to the control system. This feedback enables real-time monitoring and precise identification of failures in specific wafers, allowing for accurate diagnosis and maintenance of high-performance stacked memory systems without sacrificing data throughput.
3Measurement precision
If identification circuits are integrated into each IC substrate, then unique identification of individual layers is enabled, but device complexity increases
Solution Approach 1:
The patent merges the identification circuit functionality with the existing memory circuitry of each wafer. The identification circuits are integrated into the same substrate as the memory cells and control logic, sharing physical space and electrical infrastructure. This merging approach enables precise identification of individual layers while minimizing the increase in overall device complexity by utilizing existing structural resources.
Solution Approach 2:
The patent designs the identification circuits to be universal components that can be implemented across all wafers in the stack using the same design and fabrication processes. This universality allows for precise identification of individual layers while avoiding the complexity increase that would result from custom-designed identification circuits for each wafer. The multi-functional nature of these circuits allows them to serve both identification purposes and integrate with the memory functional requirements.
Data Source
AI summary
A semiconductor package includes a plurality of integrated circuit (IC) substrates and a conductive structure. The IC substrates are stacked one above another. The conductive structure penetrates through the IC substrates. Each of the IC substrates includes an identification circuit coupled to the conductive structure. Each identification circuit is configured to identify a corresponding IC substrate by receiving an input signal from the conductive structure and accordingly generating an identifier of the corresponding IC substrate.