Stacked IC Conductive Line Routing Without TSV Interconnects
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Solution Overview
Problem
In vertically stacked integrated circuit configurations, existing methods such as through silicon vias (TSVs) are costly and time-consuming, and wire bonding is not usable for flip-chip mounting configurations, necessitating an efficient interconnection solution between stacked devices.
Innovation Solution
The formation of conductive lines on multiple surfaces of a first device, using a subtractive process, which extends on the upper, side, and lower surfaces, allowing interconnection between a second device above and a third device below without the need for TSVs, utilizing interconnect components like solder balls or bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) are used for interconnection, then electrical coupling between stacked devices is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
Instead of forming vias through the substrate from one side, the patent forms conductive lines from the opposite side (back-side routing), inverting the conventional via approach. This allows conductive paths to be created without penetrating the substrate, eliminating the need for complex TSV formation processes while achieving the same electrical interconnection function.
Solution Approach 2:
The patent transitions from three-dimensional through-substrate via structures to two-dimensional surface-level conductive lines. By routing conductors on the back surface of the substrate rather than through it, the solution reduces structural complexity and manufacturing difficulty while maintaining electrical connectivity between stacked devices.
2Reliability
If through silicon vias (TSVs) are used for interconnection, then electrical coupling between stacked devices is achieved, but manufacturing time increases
Solution Approach 1:
The patent inverts the conventional via formation approach by creating conductive lines from the back side of the substrate rather than drilling through from the front. This inversion eliminates time-consuming deep drilling, plating, and alignment processes associated with TSVs, significantly reducing manufacturing cycle time while achieving the same electrical interconnection.
3Reliability
If wire bonding is used for interconnection, then electrical coupling is achieved, but flip-chip mounting configurations cannot be supported
Solution Approach 1:
The patent moves the conductive interconnection from the traditional wire-bonding dimension (above the chip surface) to the substrate plane dimension (back-side routing). This allows the interconnection to work with flip-chip mounting configurations where wire bonding is incompatible, as the conductive lines are formed on the substrate itself rather than requiring access to chip bonds from above.
Data Source
AI summary
A microelectronics device structure includes a device having (i) a lower surface, (ii) an upper surface opposite the lower surface, and (iii) a side surface extending between the lower surface and the upper surface. The integrated circuit structure further includes a conductive line having (i) a first section on the upper surface, (ii) a second section on the side surface, and (iii) a third section on the lower surface. In an example, the first section and the second section of the conductive line is a monolithic conductive structure, with no seam or interface between the first section and the second section. Additionally or alternatively, in an example, the second section and the third section of the conductive line is a monolithic conductive structure, with no seam or interface between the second section and the third section.