Stacked Integrated Circuit Package With Modular Substrates
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Solution Overview
Problem
The challenge lies in developing an integrated circuit package system that increases density without sacrificing reliability, yield, and height profiles, particularly in portable electronic products, where miniaturization and known good die issues pose significant obstacles.
Innovation Solution
A stacked integrated circuit and package system is implemented, where multiple integrated circuits are stacked with top and bottom substrates, electrical connectors, and encapsulants, allowing for individual die functionality testing and reduced package height through strategic attachment and molding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-die stacking is used to increase density, then circuit density is improved, but reliability deteriorates because a single defective die makes the whole package unusable
Solution Approach 1:
The patent divides the package into multiple independent modules, each containing a substrate with integrated circuits. Each module can be independently tested and replaced, so a defect in one module does not necessarily render the entire package unusable. This segmentation approach allows the system to maintain functionality even when individual components fail.
Solution Approach 2:
The patent changes the organizational parameter from a single large-scale integration to multiple smaller-scale integrations on separate substrates. By distributing circuit functions across multiple substrates rather than consolidating them in one large chip, the system achieves both high density through stacking and improved reliability through modular independence.
2Reliability
If package stacking is used to overcome known good die issues, then die functionality can be checked after packaging, but package height increases which conflicts with miniaturization requirements
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacking, arranging substrates vertically in layers. This dimensional change allows multiple functional layers to be integrated within a compact volume, maintaining small footprint while enabling post-packaging functionality verification through the stacked architecture.
Solution Approach 2:
The patent implements a nested structure where multiple substrates are stacked within a compact package housing. Each substrate layer contains integrated circuits and can be independently accessed for testing, while the overall package maintains a small external dimension. The nested arrangement allows functionality verification of individual layers without increasing the overall package height significantly.
3Quantity of substance
If wafer manufacturing reduces feature size to increase circuit density, then functionality is enhanced, but manufacturing obstacles increase due to defect density control and optical resolution limits
Solution Approach 1:
Instead of manufacturing one large high-density wafer that is difficult to produce, the patent segments the circuit design into multiple smaller wafers or chips that can be manufactured using existing processes. This segmentation bypasses the optical resolution limits and defect density control issues associated with sub-micron feature sizes on large wafers, while still achieving high overall system density through stacking.
Solution Approach 2:
The patent creates multiple copies of integrated circuits on separate substrates rather than relying on a single large-scale integration. This copying approach allows standard manufacturing processes to be used for each substrate, avoiding the manufacturing obstacles of extreme miniaturization, while the stacked arrangement of multiple copies achieves the desired high circuit density.
Data Source
AI summary
A stacked integrated circuit and package system including attaching a first top integrated circuit over an upper surface of a top substrate, attaching a second top integrated circuit over a lower surface of the top substrate, forming top electrical connectors on the lower surface of the top substrate, and connecting a bottom package to the top electrical connectors.